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radv: do not emit more non-existent registers on GFX11

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Found these by diffing the list of registers between GFX10_3 and GFX11.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16557>
This commit is contained in:
Samuel Pitoiset 2022-05-10 11:19:08 +02:00 • committed by Marge Bot
parent c5d8ef97fa
commit d88c859b4e
1 changed files with 8 additions and 5 deletions
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9
src/amd/vulkan/si_cmd_buffer.c
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@ -224,11 +224,12 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
} }
if (!has_clear_state) { if (!has_clear_state) {
if (physical_device->rad_info.gfx_level < GFX11) if (physical_device->rad_info.gfx_level < GFX11) {
radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2); radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0); radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
} }
radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
}
if (physical_device->rad_info.gfx_level <= GFX9) if (physical_device->rad_info.gfx_level <= GFX9)
radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1); radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
@ -330,6 +331,7 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
S_00B324_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8)); S_00B324_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
} }
if (device->physical_device->rad_info.gfx_level < GFX11)
radeon_set_sh_reg(cs, R_00B124_SPI_SHADER_PGM_HI_VS, radeon_set_sh_reg(cs, R_00B124_SPI_SHADER_PGM_HI_VS,
S_00B124_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8)); S_00B124_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
@ -347,7 +349,8 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
cu_mask_ps = u_bit_consecutive(0, physical_device->rad_info.min_good_cu_per_sa); cu_mask_ps = u_bit_consecutive(0, physical_device->rad_info.min_good_cu_per_sa);
if (physical_device->rad_info.gfx_level >= GFX7) { if (physical_device->rad_info.gfx_level >= GFX7) {
if (physical_device->rad_info.gfx_level >= GFX10) { if (physical_device->rad_info.gfx_level >= GFX10 &&
physical_device->rad_info.gfx_level < GFX11) {
/* Logical CUs 16 - 31 */ /* Logical CUs 16 - 31 */
ac_set_reg_cu_en(cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS, S_00B404_CU_EN(0xffff), ac_set_reg_cu_en(cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS, S_00B404_CU_EN(0xffff),
C_00B404_CU_EN, 16, &physical_device->rad_info, C_00B404_CU_EN, 16, &physical_device->rad_info,