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r600g: fix DB decompression

Browse source 
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
This commit is contained in:
Jerome Glisse 2010-08-22 17:13:58 -04:00
parent d324fcea67
commit d843bbfd3f
6 changed files with 97 additions and 75 deletions
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48
src/gallium/drivers/r600/r600_blit.c
View file

@ -149,7 +149,6 @@ struct r600_blit_states {
struct radeon_state *rasterizer;
struct radeon_state *dsa;
struct radeon_state *blend;
struct radeon_state *viewport;
struct radeon_state *cb_cntl;
struct radeon_state *config;
struct radeon_state *vgt;
@ -490,33 +489,6 @@ static struct radeon_state *r600_blit_state_blend(struct r600_screen *rscreen)
return rstate;
}
static struct radeon_state *r600_blit_state_viewport(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
if (rstate == NULL)
return NULL;
/* set states (most default value are 0 and struct already
* initialized to 0, thus avoid resetting them)
*/
rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = 0x42FA0000;
rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = 0x42FA0000;
rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = 0x42FA0000;
rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = 0xC2FA0000;
rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
return NULL;
}
return rstate;
}
static struct radeon_state *r600_blit_state_cb_cntl(struct r600_screen *rscreen)
{
struct radeon_state *rstate;
@ -604,11 +576,6 @@ static int r600_blit_states_init(struct pipe_context *ctx, struct r600_blit_stat
R600_ERR("failed creating blend state\n");
return -ENOMEM;
}
bstates->viewport = r600_blit_state_viewport(rscreen);
if (bstates->viewport == NULL) {
R600_ERR("failed creating viewport state\n");
return -ENOMEM;
}
bstates->cb_cntl = r600_blit_state_cb_cntl(rscreen);
if (bstates->cb_cntl == NULL) {
R600_ERR("failed creating cb_cntl state\n");
@ -628,7 +595,6 @@ static void r600_blit_states_destroy(struct pipe_context *ctx, struct r600_blit_
radeon_state_decref(bstates->rasterizer);
radeon_state_decref(bstates->dsa);
radeon_state_decref(bstates->blend);
radeon_state_decref(bstates->viewport);
radeon_state_decref(bstates->cb_cntl);
radeon_state_decref(bstates->config);
radeon_state_decref(bstates->vgt);
@ -663,12 +629,16 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
if (r) {
return r;
}
r = r600_texture_viewport(ctx, rtexture, level);
if (r) {
return r;
}
r = r600_blit_states_init(ctx, &bstates);
if (r) {
return r;
}
bstates.dsa->states[R600_DSA__DB_RENDER_CONTROL] = 0x000000EC;
bstates.dsa->states[R600_DSA__DB_RENDER_CONTROL] = 0x0000008C;
bstates.cb_cntl->states[R600_CB_CNTL__CB_TARGET_MASK] = 0x00000001;
/* force rebuild */
bstates.dsa->cpm4 = bstates.cb_cntl->cpm4 = 0;
@ -705,10 +675,6 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
if (r) {
goto out;
}
r = radeon_draw_set(draw, bstates.viewport);
if (r) {
goto out;
}
r = radeon_draw_set(draw, bstates.cb_cntl);
if (r) {
goto out;
@ -749,6 +715,10 @@ int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_te
if (r) {
goto out;
}
r = radeon_draw_set(draw, rtexture->viewport[level]);
if (r) {
goto out;
}
r = radeon_draw_set(draw, rtexture->scissor[level]);
if (r) {
goto out;

1
src/gallium/drivers/r600/r600_resource.h
View file

@ -59,6 +59,7 @@ struct r600_resource_texture {
struct radeon_state *scissor[PIPE_MAX_TEXTURE_LEVELS];
struct radeon_state *cb0[PIPE_MAX_TEXTURE_LEVELS];
struct radeon_state *db[PIPE_MAX_TEXTURE_LEVELS];
struct radeon_state *viewport[PIPE_MAX_TEXTURE_LEVELS];
};
void r600_init_context_resource_functions(struct r600_context *r600);

1
src/gallium/drivers/r600/r600_screen.h
View file

@ -80,6 +80,7 @@ int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture
int r600_texture_cb0(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);
/* r600_blit.c */
int r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level);

10
src/gallium/drivers/r600/r600_state.c
View file

@ -775,10 +775,10 @@ static struct radeon_state *r600_db(struct r600_context *rctx)
rtex = (struct r600_resource_texture*)state->zsbuf->texture;
rtex->tilled = 1;
rtex->array_mode = 2;
rtex->tile_type = 1;
rtex->tile_type = 0;
rtex->depth = 1;
rbuffer = &rtex->resource;
R600_ERR("DB handle %d %p %d\n", rbuffer->bo->handle, rtex, state->zsbuf->texture->format);
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
rstate->nbo = 1;
rstate->placement[0] = RADEON_GEM_DOMAIN_VRAM;
@ -1256,15 +1256,9 @@ static struct radeon_state *r600_resource(struct pipe_context *ctx,
if (r) {
return NULL;
}
format = r600_translate_colorformat(view->texture->format);
R600_ERR("DEPTH TEXTURE %d rtex %p %d 0x%02X\n", tmp->uncompressed->handle, tmp, view->texture->format, format);
format = 17;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
rstate->bo[1] = radeon_bo_incref(rscreen->rw, tmp->uncompressed);
// array_mode = tmp->array_mode;
// tile_type = tmp->tile_type;
} else {
R600_ERR("NOT DEPTH TEXTURE\n");
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
}

2
src/gallium/drivers/r600/r600_state_inlines.h
View file

@ -262,7 +262,7 @@ static INLINE uint32_t r600_translate_colorformat(enum pipe_format format)
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
return V_0280A0_COLOR_24_8;
return V_0280A0_COLOR_8_24;
/* 64-bit buffers. */
case PIPE_FORMAT_R16G16B16A16_UNORM:

110
src/gallium/drivers/r600/r600_texture.c
View file

@ -247,7 +247,7 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
trans->transfer.box = *box;
trans->transfer.stride = rtex->pitch[sr.level];
trans->offset = r600_texture_get_offset(rtex, sr.level, box->z, sr.face);
if (rtex->tilled) {
if (rtex->tilled && !rtex->depth) {
resource.target = PIPE_TEXTURE_2D;
resource.format = texture->format;
resource.width0 = box->width;
@ -303,30 +303,40 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
struct pipe_transfer* transfer)
{
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
struct r600_resource *resource;
struct radeon_bo *bo;
enum pipe_format format = transfer->resource->format;
struct r600_screen *rscreen = r600_screen(ctx->screen);
struct r600_resource_texture *rtex;
unsigned long offset = 0;
char *map;
int r;
r600_flush(ctx, 0, NULL);
if (rtransfer->linear_texture) {
resource = (struct r600_resource *)rtransfer->linear_texture;
bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
} else {
resource = (struct r600_resource *)transfer->resource;
rtex = (struct r600_resource_texture*)transfer->resource;
if (rtex->depth) {
r = r600_texture_from_depth(ctx, rtex, transfer->sr.level);
if (r) {
return NULL;
}
r600_flush(ctx, 0, NULL);
bo = rtex->uncompressed;
} else {
bo = ((struct r600_resource *)transfer->resource)->bo;
}
offset = rtransfer->offset +
transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
}
if (radeon_bo_map(rscreen->rw, resource->bo)) {
if (radeon_bo_map(rscreen->rw, bo)) {
return NULL;
}
radeon_bo_wait(rscreen->rw, resource->bo);
radeon_bo_wait(rscreen->rw, bo);
map = resource->bo->data;
if (rtransfer->linear_texture) {
return map;
}
return map + rtransfer->offset +
transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
map = bo->data;
return map + offset;
}
void r600_texture_transfer_unmap(struct pipe_context *ctx,
@ -334,14 +344,20 @@ void r600_texture_transfer_unmap(struct pipe_context *ctx,
{
struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
struct r600_screen *rscreen = r600_screen(ctx->screen);
struct r600_resource *resource;
struct r600_resource_texture *rtex;
struct radeon_bo *bo;
if (rtransfer->linear_texture) {
resource = (struct r600_resource *)rtransfer->linear_texture;
bo = ((struct r600_resource *)rtransfer->linear_texture)->bo;
} else {
resource = (struct r600_resource *)transfer->resource;
rtex = (struct r600_resource_texture*)transfer->resource;
if (rtex->depth) {
bo = rtex->uncompressed;
} else {
bo = ((struct r600_resource *)transfer->resource)->bo;
}
}
radeon_bo_unmap(rscreen->rw, resource->bo);
radeon_bo_unmap(rscreen->rw, bo);
}
struct u_resource_vtbl r600_texture_vtbl =
@ -633,7 +649,6 @@ int r600_texture_from_depth(struct pipe_context *ctx, struct r600_resource_textu
/* render a rectangle covering whole buffer to uncompress depth */
r = r600_blit_uncompress_depth(ctx, rtexture, level);
R600_ERR("---step0 %d\n", r);
if (r) {
return r;
}
@ -708,13 +723,7 @@ static struct radeon_state *r600_texture_state_cb0(struct r600_screen *rscreen,
ntype = V_0280A0_NUMBER_SRGB;
format = r600_translate_colorformat(rtexture->resource.base.b.format);
swap = r600_translate_colorswap(rtexture->resource.base.b.format);
color_info = S_0280A0_FORMAT(format) |
S_0280A0_COMP_SWAP(swap) |
S_0280A0_BLEND_CLAMP(1) |
S_0280A0_NUMBER_TYPE(ntype);
if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
R600_ERR("CB0 uncompressed texture %p (handle)%d %d 0x%02X\n", rtexture, rtexture->uncompressed->handle, rtexture->resource.base.b.format, format);
format = 17;
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
rstate->bo[1] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
rstate->bo[2] = radeon_bo_incref(rscreen->rw, rtexture->uncompressed);
@ -722,6 +731,7 @@ format = 17;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 3;
color_info = 0;
} else {
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
rstate->bo[1] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
@ -730,8 +740,12 @@ format = 17;
rstate->placement[2] = RADEON_GEM_DOMAIN_GTT;
rstate->placement[4] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 3;
color_info |= S_0280A0_SOURCE_FORMAT(1);
color_info = S_0280A0_SOURCE_FORMAT(1);
}
color_info |= S_0280A0_FORMAT(format) |
S_0280A0_COMP_SWAP(swap) |
S_0280A0_BLEND_CLAMP(1) |
S_0280A0_NUMBER_TYPE(ntype);
rstate->states[R600_CB0__CB_COLOR0_BASE] = rtexture->offset[level] >> 8;
rstate->states[R600_CB0__CB_COLOR0_INFO] = color_info;
rstate->states[R600_CB0__CB_COLOR0_SIZE] = S_028060_PITCH_TILE_MAX(pitch) |
@ -770,7 +784,6 @@ static struct radeon_state *r600_texture_state_db(struct r600_screen *rscreen,
rstate->states[R600_DB__DB_PREFETCH_LIMIT] = (rtexture->height[level] / 8) -1;
rstate->states[R600_DB__DB_DEPTH_SIZE] = S_028000_PITCH_TILE_MAX(pitch) |
S_028000_SLICE_TILE_MAX(slice);
R600_ERR("DB handle %d %p %d\n", rbuffer->bo->handle, rtexture, rbuffer->base.b.format);
rstate->bo[0] = radeon_bo_incref(rscreen->rw, rbuffer->bo);
rstate->placement[0] = RADEON_GEM_DOMAIN_GTT;
rstate->nbo = 1;
@ -796,6 +809,35 @@ int r600_texture_scissor(struct pipe_context *ctx, struct r600_resource_texture
return 0;
}
static struct radeon_state *r600_texture_state_viewport(struct r600_screen *rscreen,
struct r600_resource_texture *rtexture,
unsigned level)
{
struct radeon_state *rstate;
rstate = radeon_state(rscreen->rw, R600_VIEWPORT_TYPE, R600_VIEWPORT);
if (rstate == NULL)
return NULL;
/* set states (most default value are 0 and struct already
* initialized to 0, thus avoid resetting them)
*/
rstate->states[R600_VIEWPORT__PA_CL_VPORT_XOFFSET_0] = fui((float)rtexture->width[level]/2.0);
rstate->states[R600_VIEWPORT__PA_CL_VPORT_XSCALE_0] = fui((float)rtexture->width[level]/2.0);
rstate->states[R600_VIEWPORT__PA_CL_VPORT_YOFFSET_0] = fui((float)rtexture->height[level]/2.0);
rstate->states[R600_VIEWPORT__PA_CL_VPORT_YSCALE_0] = fui((float)-rtexture->height[level]/2.0);
rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZOFFSET_0] = 0x3F000000;
rstate->states[R600_VIEWPORT__PA_CL_VPORT_ZSCALE_0] = 0x3F000000;
rstate->states[R600_VIEWPORT__PA_CL_VTE_CNTL] = 0x0000043F;
rstate->states[R600_VIEWPORT__PA_SC_VPORT_ZMAX_0] = 0x3F800000;
if (radeon_state_pm4(rstate)) {
radeon_state_decref(rstate);
return NULL;
}
return rstate;
}
int r600_texture_cb0(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
{
struct r600_screen *rscreen = r600_screen(ctx->screen);
@ -823,3 +865,17 @@ int r600_texture_db(struct pipe_context *ctx, struct r600_resource_texture *rtex
}
return 0;
}
int r600_texture_viewport(struct pipe_context *ctx, struct r600_resource_texture *rtexture, unsigned level)
{
struct r600_screen *rscreen = r600_screen(ctx->screen);
if (rtexture->viewport[level] == NULL) {
rtexture->viewport[level] = r600_texture_state_viewport(rscreen, rtexture, level);
if (rtexture->viewport[level] == NULL) {
R600_ERR("failed to create viewport state for texture\n");
return -ENOMEM;
}
}
return 0;
}