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radeonsi: set FLUSH_ON_BINNING_TRANSITION when needed

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Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Marek Olšák 2019-07-03 22:04:30 -04:00
parent 9dbe63ceea
commit d7e80ba1e7
3 changed files with 15 additions and 3 deletions
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1
src/gallium/drivers/radeonsi/si_gfx_cs.c
View file

@ -449,6 +449,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
ctx->last_tes_sh_base = -1;
ctx->last_num_tcs_input_cp = -1;
ctx->last_ls_hs_config = -1; /* impossible value */
ctx->last_binning_enabled = -1;
ctx->prim_discard_compute_ib_initialized = false;

1
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -1061,6 +1061,7 @@ struct si_context {
int last_multi_vgt_param;
int last_rast_prim;
int last_flatshade_first;
int last_binning_enabled;
unsigned last_sc_line_stipple;
unsigned current_vs_state;
unsigned last_vs_state;

16
src/gallium/drivers/radeonsi/si_state_binning.c
View file

@ -331,12 +331,17 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) |
S_028C44_DISABLE_START_OF_PRIM(1));
S_028C44_DISABLE_START_OF_PRIM(1) |
S_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->last_binning_enabled != 0));
} else {
radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
SI_TRACKED_PA_SC_BINNER_CNTL_0,
S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
S_028C44_DISABLE_START_OF_PRIM(1));
S_028C44_DISABLE_START_OF_PRIM(1) |
S_028C44_FLUSH_ON_BINNING_TRANSITION((sctx->family == CHIP_VEGA12 ||
sctx->family == CHIP_VEGA20 ||
sctx->family >= CHIP_RAVEN2) &&
sctx->last_binning_enabled != 0));
}
unsigned db_dfsm_control = sctx->chip_class >= GFX10 ? R_028038_DB_DFSM_CONTROL
@ -347,6 +352,8 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
if (initial_cdw != sctx->gfx_cs->current.cdw)
sctx->context_roll = true;
sctx->last_binning_enabled = false;
}
void si_emit_dpbb_state(struct si_context *sctx)
@ -452,7 +459,8 @@ void si_emit_dpbb_state(struct si_context *sctx)
S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin) |
S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
S_028C44_OPTIMAL_BIN_SELECTION(1));
S_028C44_OPTIMAL_BIN_SELECTION(1) |
G_028C44_FLUSH_ON_BINNING_TRANSITION(sctx->last_binning_enabled != 1));
unsigned db_dfsm_control = sctx->chip_class >= GFX10 ? R_028038_DB_DFSM_CONTROL
: R_028060_DB_DFSM_CONTROL;
@ -462,4 +470,6 @@ void si_emit_dpbb_state(struct si_context *sctx)
S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
if (initial_cdw != sctx->gfx_cs->current.cdw)
sctx->context_roll = true;
sctx->last_binning_enabled = true;
}