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nak: add support for nir_op_unpack_half_2x16_split_{x|y}
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24998>
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3 changed files with 28 additions and 0 deletions
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@ -717,6 +717,11 @@ impl SM75Instr {
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ALUSrc::from_src(&op.src.into()),
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ALUSrc::None,
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);
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if op.high {
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self.set_field(60..62, 1_u8); // .H1
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}
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self.set_field(75..77, (op.dst_type.bits() / 8).ilog2());
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self.set_rnd_mode(78..80, op.rnd_mode);
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self.set_bit(80, op.ftz);
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@ -368,6 +368,7 @@ impl<'a> ShaderFromNir<'a> {
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dst_type: FloatType::F16,
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rnd_mode: FRndMode::NearestEven,
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ftz: true,
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high: false,
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});
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assert!(alu.def.bit_size() == 32);
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let dst = b.alloc_ssa(RegFile::GPR, 1);
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@ -378,6 +379,7 @@ impl<'a> ShaderFromNir<'a> {
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dst_type: FloatType::F32,
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rnd_mode: FRndMode::NearestEven,
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ftz: true,
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high: false,
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});
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dst
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}
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@ -677,6 +679,7 @@ impl<'a> ShaderFromNir<'a> {
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dst_type: FloatType::F16,
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rnd_mode: FRndMode::NearestEven,
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ftz: false,
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high: false,
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});
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let src_bits = usize::from(alu.get_src(1).bit_size());
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@ -689,6 +692,7 @@ impl<'a> ShaderFromNir<'a> {
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dst_type: FloatType::F16,
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rnd_mode: FRndMode::NearestEven,
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ftz: false,
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high: false,
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});
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let dst = b.alloc_ssa(RegFile::GPR, 1);
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@ -742,6 +746,23 @@ impl<'a> ShaderFromNir<'a> {
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let src0_y = srcs[0].as_ssa().unwrap()[1];
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b.mov(src0_y.into())
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}
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nir_op_unpack_half_2x16_split_x
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| nir_op_unpack_half_2x16_split_y => {
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assert!(alu.def.bit_size() == 32);
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let dst = b.alloc_ssa(RegFile::GPR, 1);
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b.push_op(OpF2F {
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dst: dst[0].into(),
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src: srcs[0],
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src_type: FloatType::F16,
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dst_type: FloatType::F32,
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rnd_mode: FRndMode::NearestEven,
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ftz: false,
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high: alu.op == nir_op_unpack_half_2x16_split_y,
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});
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dst
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}
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nir_op_ushr => {
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assert!(alu.def.bit_size() == 32);
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let dst = b.alloc_ssa(RegFile::GPR, 1);
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@ -2100,6 +2100,8 @@ pub struct OpF2F {
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pub dst_type: FloatType,
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pub rnd_mode: FRndMode,
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pub ftz: bool,
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/// Place the result into the upper 16 bits of the destination register
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pub high: bool,
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}
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impl fmt::Display for OpF2F {
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