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brw: Support load_simd_width_intel for fragment shaders

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This lets us emit NIR code based on the SIMD size.  For non-fragment
stages, we'll replace it with a constant and optimize, but for FS,
we delay it until the backend.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40843>
This commit is contained in:
Kenneth Graunke 2026-04-08 01:24:29 -07:00 • committed by Marge Bot
parent cac9f670d1
commit d7d2d7aceb
1 changed files with 1 additions and 0 deletions
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src/intel/compiler/brw/brw_from_nir.cpp
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@ -5467,6 +5467,7 @@ brw_from_nir_emit_intrinsic(nir_to_brw_state &ntb,
}
case nir_intrinsic_load_subgroup_size:
case nir_intrinsic_load_simd_width_intel:
/* This should only happen for fragment shaders because every other case
* is lowered in NIR so we can optimize on it.
*/