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ac/gpu_info: add payload_entry_size into ac_task_info

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to stop causing full RADV recompiles when it's changed.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34432>
This commit is contained in:
Marek Olšák 2025-04-07 22:05:31 -04:00 • committed by Marge Bot
parent 0dafd04695
commit d7c903f258
4 changed files with 10 additions and 9 deletions
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7
src/amd/common/ac_gpu_info.c
View file

@ -2499,11 +2499,16 @@ static uint16_t get_task_num_entries(enum radeon_family fam)
void ac_get_task_info(const struct radeon_info *info,
struct ac_task_info *task_info)
{
/* Size of each payload entry in the task payload ring.
* Spec requires minimum 16K bytes.
*/
const uint32_t payload_entry_size = 16384;
const uint16_t num_entries = get_task_num_entries(info->family);
const uint32_t draw_ring_bytes = num_entries * AC_TASK_DRAW_ENTRY_BYTES;
const uint32_t payload_ring_bytes = num_entries * AC_TASK_PAYLOAD_ENTRY_BYTES;
const uint32_t payload_ring_bytes = num_entries * payload_entry_size;
/* Ensure that the addresses of each ring are 256 byte aligned. */
task_info->payload_entry_size = payload_entry_size;
task_info->num_entries = num_entries;
task_info->draw_ring_offset = ALIGN(AC_TASK_CTRLBUF_BYTES, 256);
task_info->payload_ring_offset = ALIGN(task_info->draw_ring_offset + draw_ring_bytes, 256);

6
src/amd/common/ac_gpu_info.h
View file

@ -382,13 +382,9 @@ struct ac_task_info {
uint32_t payload_ring_offset;
uint32_t bo_size_bytes;
uint16_t num_entries;
uint32_t payload_entry_size;
};
/* Size of each payload entry in the task payload ring.
* Spec requires minimum 16K bytes.
*/
#define AC_TASK_PAYLOAD_ENTRY_BYTES 16384
/* Size of each draw entry in the task draw ring.
* 4 DWORDs per entry.
*/

4
src/amd/vulkan/nir/radv_nir_lower_io.c
View file

@ -254,11 +254,11 @@ radv_nir_lower_io_to_mem(struct radv_device *device, struct radv_shader_stage *s
NIR_PASS(_, nir, ac_nir_lower_gs_inputs_to_mem, map_input, pdev->info.gfx_level, false);
return true;
} else if (nir->info.stage == MESA_SHADER_TASK) {
ac_nir_lower_task_outputs_to_mem(nir, AC_TASK_PAYLOAD_ENTRY_BYTES, pdev->task_info.num_entries,
ac_nir_lower_task_outputs_to_mem(nir, pdev->task_info.payload_entry_size, pdev->task_info.num_entries,
info->cs.has_query);
return true;
} else if (nir->info.stage == MESA_SHADER_MESH) {
ac_nir_lower_mesh_inputs_to_mem(nir, AC_TASK_PAYLOAD_ENTRY_BYTES, pdev->task_info.num_entries);
ac_nir_lower_mesh_inputs_to_mem(nir, pdev->task_info.payload_entry_size, pdev->task_info.num_entries);
return true;
}

2
src/amd/vulkan/radv_queue.c
View file

@ -326,7 +326,7 @@ radv_fill_shader_rings(struct radv_device *device, uint32_t *desc, struct radeon
pdev->task_info.num_entries * AC_TASK_DRAW_ENTRY_BYTES, false, false, false, 0, 0, &desc[0]);
radv_set_ring_buffer(pdev, task_rings_bo, pdev->task_info.payload_ring_offset,
pdev->task_info.num_entries * AC_TASK_PAYLOAD_ENTRY_BYTES, false, false, false, 0, 0,
pdev->task_info.num_entries * pdev->task_info.payload_entry_size, false, false, false, 0, 0,
&desc[4]);
}