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radeonsi: use the optimal draw packet sequence for VGT_FLUSH
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13048>
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@ -2267,7 +2267,7 @@ static void si_draw_vbo(struct pipe_context *ctx,
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/* Use optimal packet order based on whether we need to sync the pipeline. */
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if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB |
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SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH |
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SI_CONTEXT_VS_PARTIAL_FLUSH))) {
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SI_CONTEXT_VS_PARTIAL_FLUSH | SI_CONTEXT_VGT_FLUSH))) {
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/* If we have to wait for idle, set all states first, so that all
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* SET packets are processed in parallel with previous draw calls.
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* Then draw and prefetch at the end. This ensures that the time
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