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radeonsi: clarify shader constant load functions
I'll need indexed loads without the meta data flag for tessellation later. Also rename load_const to buffer_load_const to distinguish it from indexed const loads. v2: add comments Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák
parent
55a9b778c8
commit
d787608957
1 changed files with 46 additions and 40 deletions
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@ -182,32 +182,35 @@ static int get_param_index(unsigned semantic_name, unsigned index,
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}
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/**
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* Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
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*
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* @param offset The offset parameter specifies the number of
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* elements to offset, not the number of bytes or dwords. An element is the
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* the type pointed to by the base_ptr parameter (e.g. int is the element of
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* an int* pointer)
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*
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* When LLVM lowers the load instruction, it will convert the element offset
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* into a dword offset automatically.
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* Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
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* It's equivalent to doing a load from &base_ptr[index].
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*
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* \param base_ptr Where the array starts.
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* \param index The element index into the array.
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*/
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static LLVMValueRef build_indexed_load(
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struct si_shader_context * si_shader_ctx,
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LLVMValueRef base_ptr,
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LLVMValueRef offset)
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static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
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LLVMValueRef base_ptr, LLVMValueRef index)
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{
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struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
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struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
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struct gallivm_state *gallivm = bld_base->base.gallivm;
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LLVMValueRef indices[2], pointer;
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LLVMValueRef indices[2] = {
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LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, false),
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offset
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};
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LLVMValueRef computed_ptr = LLVMBuildGEP(
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base->gallivm->builder, base_ptr, indices, 2, "");
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indices[0] = bld_base->uint_bld.zero;
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indices[1] = index;
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LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
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pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
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return LLVMBuildLoad(gallivm->builder, pointer, "");
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}
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/**
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* Do a load from &base_ptr[index], but also add a flag that it's loading
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* a constant.
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*/
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static LLVMValueRef build_indexed_load_const(
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struct si_shader_context * si_shader_ctx,
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LLVMValueRef base_ptr, LLVMValueRef index)
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{
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LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
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LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
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return result;
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}
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@ -259,7 +262,7 @@ static void declare_input_vs(
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t_offset = lp_build_const_int32(gallivm, input_index);
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t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
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t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
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/* Build the attribute offset */
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attribute_offset = lp_build_const_int32(gallivm, 0);
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@ -354,7 +357,7 @@ static LLVMValueRef fetch_input_gs(
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/* Load the ESGS ring resource descriptor */
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t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
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SI_PARAM_RW_BUFFERS);
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t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
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t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr,
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lp_build_const_int32(gallivm, SI_RING_ESGS));
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args[0] = t_list;
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@ -562,8 +565,11 @@ static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
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return value;
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}
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static LLVMValueRef load_const(LLVMBuilderRef builder, LLVMValueRef resource,
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LLVMValueRef offset, LLVMTypeRef return_type)
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/**
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* Load a dword from a constant buffer.
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*/
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static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
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LLVMValueRef offset, LLVMTypeRef return_type)
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{
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LLVMValueRef args[2] = {resource, offset};
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@ -602,15 +608,15 @@ static void declare_system_value(
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LLVMBuilderRef builder = gallivm->builder;
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LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
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LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
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LLVMValueRef resource = build_indexed_load(si_shader_ctx, desc, buf_index);
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LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
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/* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
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LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, get_sample_id(radeon_bld), 8);
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LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
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LLVMValueRef pos[4] = {
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load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
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load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
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buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
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buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
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lp_build_const_float(gallivm, 0),
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lp_build_const_float(gallivm, 0)
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};
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@ -661,7 +667,7 @@ static LLVMValueRef fetch_constant(
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addr = lp_build_add(&bld_base->uint_bld, addr,
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lp_build_const_int32(base->gallivm, idx * 4));
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result = load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
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result = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
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addr, base->elem_type);
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return bitcast(bld_base, type, result);
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@ -812,7 +818,7 @@ static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
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LLVMValueRef base_elt;
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LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
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LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
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LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, constbuf_index);
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LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
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for (reg_index = 0; reg_index < 2; reg_index ++) {
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LLVMValueRef *args = pos[2 + reg_index];
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@ -830,7 +836,7 @@ static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
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args[1] = lp_build_const_int32(base->gallivm,
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((reg_index * 4 + chan) * 4 +
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const_chan) * 4);
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base_elt = load_const(base->gallivm->builder, const_resource,
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base_elt = buffer_load_const(base->gallivm->builder, const_resource,
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args[1], base->elem_type);
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args[5 + chan] =
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lp_build_add(base, args[5 + chan],
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@ -1242,7 +1248,7 @@ static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
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/* Load the ESGS ring resource descriptor */
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t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
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SI_PARAM_RW_BUFFERS);
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t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
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t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr,
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lp_build_const_int32(gallivm, SI_RING_ESGS));
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for (i = 0; i < info->num_outputs; i++) {
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@ -2153,7 +2159,7 @@ static void si_llvm_emit_vertex(
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/* Load the GSVS ring resource descriptor */
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t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
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SI_PARAM_RW_BUFFERS);
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t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
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t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr,
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lp_build_const_int32(gallivm, SI_RING_GSVS));
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/* Write vertex attribute values to GSVS ring */
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@ -2408,12 +2414,12 @@ static void preload_constants(struct si_shader_context *si_shader_ctx)
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/* Load the resource descriptor */
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si_shader_ctx->const_resource[buf] =
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build_indexed_load(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
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build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
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/* Load the constants, we rely on the code sinking to do the rest */
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for (i = 0; i < num_const * 4; ++i) {
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si_shader_ctx->constants[buf][i] =
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load_const(gallivm->builder,
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buffer_load_const(gallivm->builder,
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si_shader_ctx->const_resource[buf],
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lp_build_const_int32(gallivm, i * 4),
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bld_base->base.elem_type);
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@ -2442,17 +2448,17 @@ static void preload_samplers(struct si_shader_context *si_shader_ctx)
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for (i = 0; i < num_samplers; ++i) {
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/* Resource */
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offset = lp_build_const_int32(gallivm, i);
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si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
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si_shader_ctx->resources[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
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/* Sampler */
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offset = lp_build_const_int32(gallivm, i);
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si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
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si_shader_ctx->samplers[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
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/* FMASK resource */
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if (info->is_msaa_sampler[i]) {
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offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
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si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
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build_indexed_load(si_shader_ctx, res_ptr, offset);
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build_indexed_load_const(si_shader_ctx, res_ptr, offset);
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}
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}
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}
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@ -2477,7 +2483,7 @@ static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
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LLVMValueRef offset = lp_build_const_int32(gallivm,
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SI_SO_BUF_OFFSET + i);
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si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
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si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
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}
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}
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}
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@ -2599,7 +2605,7 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen,
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/* Load the GSVS ring resource descriptor */
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t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
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SI_PARAM_RW_BUFFERS);
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t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
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t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr,
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lp_build_const_int32(gallivm, SI_RING_GSVS));
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args[0] = t_list;
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