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radeonsi/gfx9: indirect buffers and all CP packets use TC L2

Browse source 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-06-06 12:13:40 +02:00
parent 2638250fec
commit d7141d8bc0
4 changed files with 21 additions and 13 deletions
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5
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -788,8 +788,9 @@ static void si_launch_grid(
if (info->indirect) {
r600_context_add_resource_size(ctx, info->indirect);
/* The hw doesn't read the indirect buffer via TC L2. */
if (r600_resource(info->indirect)->TC_L2_dirty) {
/* Indirect buffers use TC L2 on GFX9, but not older hw. */
if (sctx->b.chip_class <= VI &&
r600_resource(info->indirect)->TC_L2_dirty) {
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
r600_resource(info->indirect)->TC_L2_dirty = false;
}

6
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -1010,8 +1010,10 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
(sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
sscreen->b.barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
SI_CONTEXT_INV_VMEM_L1 |
SI_CONTEXT_INV_GLOBAL_L2;
SI_CONTEXT_INV_VMEM_L1;
if (sscreen->b.chip_class <= VI)
sscreen->b.barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
sscreen->b.barrier_flags.compute_to_L2 = SI_CONTEXT_CS_PARTIAL_FLUSH;
if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))

4
src/gallium/drivers/radeonsi/si_state.c
View file

@ -4023,7 +4023,9 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
SI_CONTEXT_WRITEBACK_GLOBAL_L2;
}
if (flags & PIPE_BARRIER_INDIRECT_BUFFER)
/* Indirect buffers use TC L2 on GFX9, but not older hw. */
if (sctx->screen->b.chip_class <= VI &&
flags & PIPE_BARRIER_INDIRECT_BUFFER)
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
}

19
src/gallium/drivers/radeonsi/si_state_draw.c
View file

@ -1320,15 +1320,18 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
/* Add the buffer size for memory checking in need_cs_space. */
r600_context_add_resource_size(ctx, indirect->buffer);
if (r600_resource(indirect->buffer)->TC_L2_dirty) {
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
r600_resource(indirect->buffer)->TC_L2_dirty = false;
}
/* Indirect buffers use TC L2 on GFX9, but not older hw. */
if (sctx->b.chip_class <= VI) {
if (r600_resource(indirect->buffer)->TC_L2_dirty) {
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
r600_resource(indirect->buffer)->TC_L2_dirty = false;
}
if (indirect->indirect_draw_count &&
r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
if (indirect->indirect_draw_count &&
r600_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
r600_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
}
}
}