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freedreno/registers: correct WFM bit in CP_REG_TEST

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21151>
This commit is contained in:
Chia-I Wu 2023-02-06 14:27:46 -08:00 • committed by Marge Bot
parent dda85cf94b
commit d6fb4d8d7d
5 changed files with 17 additions and 17 deletions
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22
src/freedreno/.gitlab-ci/reference/fd-clouds.log
View file

@ -1471,7 +1471,7 @@ cmdstream[0]: 1023 dwords
gpuaddr:0000000001d90010
0000000001d918e0: 0000: 70c28003 00000883 01d90010 00000000
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
0000000001d918f0: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | MODE = PRED_TEST }
@ -1553,7 +1553,7 @@ cmdstream[0]: 1023 dwords
opcode: CP_SET_MODE (63) (2 dwords)
0000000001d919d0: 0000: 70e30001 00000000
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
0000000001d919d8: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | MODE = PRED_TEST }
@ -1703,7 +1703,7 @@ cmdstream[0]: 1023 dwords
:0,1,17,6
0000000001d91aa4: 0000: 48088901 00000011
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0xc38 | BIT = 0 | WAIT_FOR_ME }
{ REG = 0xc38 | BIT = 0 | SKIP_WAIT_FOR_ME }
0000000001d91aac: 0000: 70b90001 02000c38
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | MODE = PRED_TEST }
@ -6745,7 +6745,7 @@ cmdstream[0]: 1023 dwords
:0,1,18,3
0000000001d91ad4: 0000: 48088901 00000012
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
0000000001d91adc: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | MODE = PRED_TEST }
@ -6870,7 +6870,7 @@ cmdstream[0]: 1023 dwords
opcode: CP_SET_MODE (63) (2 dwords)
0000000001d91b9c: 0000: 70e30001 00000000
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
0000000001d91ba4: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | MODE = PRED_TEST }
@ -6944,7 +6944,7 @@ cmdstream[0]: 1023 dwords
:0,1,27,24
0000000001d91c70: 0000: 48088901 0000001b
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0xc39 | BIT = 0 | WAIT_FOR_ME }
{ REG = 0xc39 | BIT = 0 | SKIP_WAIT_FOR_ME }
0000000001d91c78: 0000: 70b90001 02000c39
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | MODE = PRED_TEST }
@ -6961,7 +6961,7 @@ cmdstream[0]: 1023 dwords
:0,1,28,24
0000000001d91ca0: 0000: 48088901 0000001c
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
0000000001d91ca8: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | MODE = PRED_TEST }
@ -7039,7 +7039,7 @@ cmdstream[0]: 1023 dwords
opcode: CP_SET_MODE (63) (2 dwords)
0000000001d91d68: 0000: 70e30001 00000000
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
0000000001d91d70: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | MODE = PRED_TEST }
@ -7113,7 +7113,7 @@ cmdstream[0]: 1023 dwords
:0,1,37,34
0000000001d91e3c: 0000: 48088901 00000025
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0xc3a | BIT = 0 | WAIT_FOR_ME }
{ REG = 0xc3a | BIT = 0 | SKIP_WAIT_FOR_ME }
0000000001d91e44: 0000: 70b90001 02000c3a
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | MODE = PRED_TEST }
@ -7130,7 +7130,7 @@ cmdstream[0]: 1023 dwords
:0,1,38,34
0000000001d91e6c: 0000: 48088901 00000026
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
0000000001d91e74: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | MODE = PRED_TEST }
@ -7208,7 +7208,7 @@ cmdstream[0]: 1023 dwords
opcode: CP_SET_MODE (63) (2 dwords)
0000000001d91f34: 0000: 70e30001 00000000
opcode: CP_REG_TEST (39) (2 dwords)
{ REG = 0x883 | BIT = 0 | WAIT_FOR_ME }
{ REG = 0x883 | BIT = 0 | SKIP_WAIT_FOR_ME }
0000000001d91f3c: 0000: 70b90001 02000883
opcode: CP_COND_REG_EXEC (47) (3 dwords)
{ REG0 = 0 | MODE = PRED_TEST }

4
src/freedreno/registers/adreno/adreno_pm4.xml
View file

@ -1721,8 +1721,8 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<bitfield name="REG" low="0" high="17"/>
<!-- the bit to test -->
<bitfield name="BIT" low="20" high="24" type="uint"/>
<!-- execute CP_WAIT_FOR_ME beforehand -->
<bitfield name="WAIT_FOR_ME" pos="25" type="boolean"/>
<!-- skip implied CP_WAIT_FOR_ME -->
<bitfield name="SKIP_WAIT_FOR_ME" pos="25" type="boolean"/>
<!--
Appears only in:
opcode: CP_REG_TEST (39) (4 dwords)

4
src/freedreno/vulkan/tu_cmd_buffer.c
View file

@ -734,13 +734,13 @@ use_sysmem_rendering(struct tu_cmd_buffer *cmd,
*/
static void
tu6_emit_cond_for_load_stores(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
uint32_t pipe, uint32_t slot, bool wfm)
uint32_t pipe, uint32_t slot, bool skip_wfm)
{
if (cmd->state.tiling->binning_possible) {
tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(pipe)) |
A6XX_CP_REG_TEST_0_BIT(slot) |
COND(wfm, A6XX_CP_REG_TEST_0_WAIT_FOR_ME));
COND(skip_wfm, A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME));
} else {
/* COND_REG_EXECs are not emitted in non-binning case */
}

2
src/freedreno/vulkan/tu_query.c
View file

@ -897,7 +897,7 @@ emit_perfcntrs_pass_start(struct tu_cs *cs, uint32_t pass)
tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(
REG_A6XX_CP_SCRATCH_REG(PERF_CNTRS_REG)) |
A6XX_CP_REG_TEST_0_BIT(pass) |
A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME);
tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(PRED_TEST));
}

2
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
View file

@ -652,7 +652,7 @@ emit_conditional_ib(struct fd_batch *batch, const struct fd_tile *tile,
OUT_PKT7(ring, CP_REG_TEST, 1);
OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(tile->p)) |
A6XX_CP_REG_TEST_0_BIT(tile->n) |
A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME);
OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
OUT_RING(ring, CP_COND_REG_EXEC_0_MODE(PRED_TEST));