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amd/addrlib: add support for VegaM

Browse source 
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-11-07 02:00:03 +01:00
parent d15fb766aa
commit d6a66bc8db
4 changed files with 41 additions and 0 deletions
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2
src/amd/addrlib/amdgpu_asic_addr.h
View file

@ -79,6 +79,7 @@
#define AMDGPU_POLARIS10_RANGE 0x50, 0x5A #define AMDGPU_POLARIS10_RANGE 0x50, 0x5A
#define AMDGPU_POLARIS11_RANGE 0x5A, 0x64 #define AMDGPU_POLARIS11_RANGE 0x5A, 0x64
#define AMDGPU_POLARIS12_RANGE 0x64, 0x6E #define AMDGPU_POLARIS12_RANGE 0x64, 0x6E
#define AMDGPU_VEGAM_RANGE 0x6E, 0xFF
#define AMDGPU_CARRIZO_RANGE 0x01, 0x21 #define AMDGPU_CARRIZO_RANGE 0x01, 0x21
#define AMDGPU_BRISTOL_RANGE 0x10, 0x21 #define AMDGPU_BRISTOL_RANGE 0x10, 0x21
@ -117,6 +118,7 @@
#define ASICREV_IS_POLARIS10_P(r) ASICREV_IS(r, POLARIS10) #define ASICREV_IS_POLARIS10_P(r) ASICREV_IS(r, POLARIS10)
#define ASICREV_IS_POLARIS11_M(r) ASICREV_IS(r, POLARIS11) #define ASICREV_IS_POLARIS11_M(r) ASICREV_IS(r, POLARIS11)
#define ASICREV_IS_POLARIS12_V(r) ASICREV_IS(r, POLARIS12) #define ASICREV_IS_POLARIS12_V(r) ASICREV_IS(r, POLARIS12)
#define ASICREV_IS_VEGAM_P(r) ASICREV_IS(r, VEGAM)
#define ASICREV_IS_CARRIZO(r) ASICREV_IS(r, CARRIZO) #define ASICREV_IS_CARRIZO(r) ASICREV_IS(r, CARRIZO)
#define ASICREV_IS_CARRIZO_BRISTOL(r) ASICREV_IS(r, BRISTOL) #define ASICREV_IS_CARRIZO_BRISTOL(r) ASICREV_IS(r, BRISTOL)

5
src/amd/addrlib/r800/ciaddrlib.cpp
View file

@ -401,6 +401,7 @@ ChipFamily CiLib::HwlConvertChipFamily(
m_settings.isPolaris10 = ASICREV_IS_POLARIS10_P(uChipRevision); m_settings.isPolaris10 = ASICREV_IS_POLARIS10_P(uChipRevision);
m_settings.isPolaris11 = ASICREV_IS_POLARIS11_M(uChipRevision); m_settings.isPolaris11 = ASICREV_IS_POLARIS11_M(uChipRevision);
m_settings.isPolaris12 = ASICREV_IS_POLARIS12_V(uChipRevision); m_settings.isPolaris12 = ASICREV_IS_POLARIS12_V(uChipRevision);
m_settings.isVegaM = ASICREV_IS_VEGAM_P(uChipRevision);
family = ADDR_CHIP_FAMILY_VI; family = ADDR_CHIP_FAMILY_VI;
break; break;
case FAMILY_CZ: case FAMILY_CZ:
@ -470,6 +471,10 @@ BOOL_32 CiLib::HwlInitGlobalParams(
{ {
m_pipes = 4; m_pipes = 4;
} }
else if (m_settings.isVegaM)
{
m_pipes = 16;
}
if (valid) if (valid)
{ {

33
src/amd/addrlib/r800/siaddrlib.cpp
View file

@ -611,6 +611,29 @@ ADDR_E_RETURNCODE SiLib::ComputePipeEquation(
break; break;
} }
if (m_settings.isVegaM && (pEquation->numBits == 4))
{
ADDR_CHANNEL_SETTING addeMsb = pAddr[0];
ADDR_CHANNEL_SETTING xor1Msb = pXor1[0];
ADDR_CHANNEL_SETTING xor2Msb = pXor2[0];
pAddr[0] = pAddr[1];
pXor1[0] = pXor1[1];
pXor2[0] = pXor2[1];
pAddr[1] = pAddr[2];
pXor1[1] = pXor1[2];
pXor2[1] = pXor2[2];
pAddr[2] = pAddr[3];
pXor1[2] = pXor1[3];
pXor2[2] = pXor2[3];
pAddr[3] = addeMsb;
pXor1[3] = xor1Msb;
pXor2[3] = xor2Msb;
}
for (UINT_32 i = 0; i < pEquation->numBits; i++) for (UINT_32 i = 0; i < pEquation->numBits; i++)
{ {
if (pAddr[i].value == 0) if (pAddr[i].value == 0)
@ -754,6 +777,16 @@ UINT_32 SiLib::ComputePipeFromCoord(
ADDR_UNHANDLED_CASE(); ADDR_UNHANDLED_CASE();
break; break;
} }
if (m_settings.isVegaM && (numPipes == 16))
{
UINT_32 pipeMsb = pipeBit0;
pipeBit0 = pipeBit1;
pipeBit1 = pipeBit2;
pipeBit2 = pipeBit3;
pipeBit3 = pipeMsb;
}
pipe = pipeBit0 | (pipeBit1 << 1) | (pipeBit2 << 2) | (pipeBit3 << 3); pipe = pipeBit0 | (pipeBit1 << 1) | (pipeBit2 << 2) | (pipeBit3 << 3);
UINT_32 microTileThickness = Thickness(tileMode); UINT_32 microTileThickness = Thickness(tileMode);

1
src/amd/addrlib/r800/siaddrlib.h
View file

@ -87,6 +87,7 @@ struct SiChipSettings
UINT_32 isPolaris10 : 1; UINT_32 isPolaris10 : 1;
UINT_32 isPolaris11 : 1; UINT_32 isPolaris11 : 1;
UINT_32 isPolaris12 : 1; UINT_32 isPolaris12 : 1;
UINT_32 isVegaM : 1;
// VI fusion // VI fusion
UINT_32 isCarrizo : 1; UINT_32 isCarrizo : 1;
}; };