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radv: Disable coherent L2 optimization on cards with noncoherent L2.

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With high likelihood we are forgetting to set the noncoherent bits
somewhere but I don't have the HW to debug. To avoid user pain
disable this optimization on these GPUs.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5505
Fixes: fd8210f27e ("radv: Try to do a better job of dealing with L2 coherent images.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13620>
This commit is contained in:
Bas Nieuwenhuizen 2021-11-01 16:39:50 +01:00 • committed by Marge Bot
parent 65afcddbf1
commit d66514aacc
1 changed files with 11 additions and 4 deletions
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15
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -3742,6 +3742,14 @@ radv_stage_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags src_st
}
}
static bool
can_skip_buffer_l2_flushes(struct radv_device *device)
{
return device->physical_device->rad_info.chip_class == GFX9 ||
(device->physical_device->rad_info.chip_class >= GFX10 &&
!device->physical_device->rad_info.tcc_rb_non_coherent);
}
/*
* In vulkan barriers have two kinds of operations:
*
@ -3873,8 +3881,8 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags dst_flag
/* All the L2 invalidations below are not the CB/DB. So if there are no incoherent images
* in the L2 cache in CB/DB mode then they are already usable from all the other L2 clients. */
image_is_coherent |= cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&
!cmd_buffer->state.rb_noncoherent_dirty;
image_is_coherent |=
can_skip_buffer_l2_flushes(cmd_buffer->device) && !cmd_buffer->state.rb_noncoherent_dirty;
u_foreach_bit(b, dst_flags)
{
@ -4765,8 +4773,7 @@ radv_EndCommandBuffer(VkCommandBuffer commandBuffer)
/* Flush noncoherent images on GFX9+ so we can assume they're clean on the start of a
* command buffer.
*/
if (cmd_buffer->state.rb_noncoherent_dirty &&
cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
if (cmd_buffer->state.rb_noncoherent_dirty && can_skip_buffer_l2_flushes(cmd_buffer->device))
cmd_buffer->state.flush_bits |= radv_src_access_flush(
cmd_buffer,
VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT | VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT,