diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index f9d698b06a9..be7dd876af2 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -2495,7 +2495,7 @@ vec4_visitor::run()
    bool allocated_without_spills = reg_allocate();
 
    if (!allocated_without_spills) {
-      brw_shader_perf_log(compiler, params->log_data,
+      brw_shader_perf_log(compiler, log_data,
                           "%s shader triggered register spilling.  "
                           "Try reducing the number of live vec4 values "
                           "to improve performance.\n",
diff --git a/src/intel/compiler/brw_vec4.h b/src/intel/compiler/brw_vec4.h
index 5ab95673924..a13c3228d08 100644
--- a/src/intel/compiler/brw_vec4.h
+++ b/src/intel/compiler/brw_vec4.h
@@ -342,8 +342,6 @@ private:
    const bool no_spills;
 
    unsigned last_scratch; /**< measured in 32-byte (register size) units */
-
-   const struct brw_compile_params *params;
 };
 
 } /* namespace brw */