From d622e19f000c7c26b6788a41375c1f0ea920c33d Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Fri, 1 Dec 2023 21:51:19 -0800 Subject: [PATCH] intel/fs/xe2+: Enable new format of barycentrics in PS payload. The X and Y barycentric vectors are no longer interleaved in SIMD8 chunks (yay), so this is mostly a matter of disabling the lower_barycentrics() pass and switching to a simpler implementation of fetch_barycentric_reg() that simply calls fetch_payload_reg() instead of the SIMD8 shuffling we had to do in previous generations. Reviewed-by: Caio Oliveira Reviewed-by: Jordan Justen Part-of: --- src/intel/compiler/brw_fs.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 6924aebbcd6..dedcfd56952 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -5500,7 +5500,8 @@ fs_visitor::lower_simd_width() bool fs_visitor::lower_barycentrics() { - const bool has_interleaved_layout = devinfo->has_pln || devinfo->ver >= 7; + const bool has_interleaved_layout = devinfo->has_pln || + (devinfo->ver >= 7 && devinfo->ver < 20); bool progress = false; if (stage != MESA_SHADER_FRAGMENT || !has_interleaved_layout) @@ -8367,6 +8368,8 @@ namespace brw { { if (!regs[0]) return fs_reg(); + else if (bld.shader->devinfo->ver >= 20) + return fetch_payload_reg(bld, regs, BRW_REGISTER_TYPE_F, 2); const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_F, 2); const brw::fs_builder hbld = bld.exec_all().group(8, 0);