From d61d6fc3bc1c9c965ff640530111112a2aa8d911 Mon Sep 17 00:00:00 2001 From: Caio Oliveira Date: Fri, 16 Feb 2024 14:52:03 -0800 Subject: [PATCH] intel/brw: Remove Gfx8- code from EU codegen helpers Reviewed-by: Kenneth Graunke Part-of: --- src/intel/compiler/brw_disasm.c | 4 +- src/intel/compiler/brw_eu.c | 41 +--- src/intel/compiler/brw_eu.h | 385 ++++++-------------------------- 3 files changed, 67 insertions(+), 363 deletions(-) diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index ae43f2cf3f6..b4d704c20f8 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/compiler/brw_disasm.c @@ -2182,7 +2182,7 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, case GFX6_SFID_DATAPORT_RENDER_CACHE: { /* aka BRW_SFID_DATAPORT_WRITE on Gfx4-5 */ - unsigned msg_type = brw_fb_write_desc_msg_type(devinfo, imm_desc); + unsigned msg_type = brw_fb_desc_msg_type(devinfo, imm_desc); err |= control(file, "DP rc message type", dp_rc_msg_type(devinfo), msg_type, &space); @@ -2202,7 +2202,7 @@ brw_disassemble_inst(FILE *file, const struct brw_isa_info *isa, string(file, " CoarseWrite"); } else { format(file, " MsgCtrl = 0x%u", - brw_fb_write_desc_msg_control(devinfo, imm_desc)); + brw_fb_desc_msg_control(devinfo, imm_desc)); } format(file, " Surface = %u", diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c index efc37665bcd..922f7c4e769 100644 --- a/src/intel/compiler/brw_eu.c +++ b/src/intel/compiler/brw_eu.c @@ -220,26 +220,11 @@ brw_inst_set_group(const struct intel_device_info *devinfo, assert(group % 8 == 0 && group < 32); brw_inst_set_qtr_control(devinfo, inst, group / 8); - } else if (devinfo->ver >= 7) { + } else { assert(group % 4 == 0 && group < 32); brw_inst_set_qtr_control(devinfo, inst, group / 8); brw_inst_set_nib_control(devinfo, inst, (group / 4) % 2); - } else if (devinfo->ver == 6) { - assert(group % 8 == 0 && group < 32); - brw_inst_set_qtr_control(devinfo, inst, group / 8); - - } else { - assert(group % 8 == 0 && group < 16); - /* The channel group and compression controls are non-orthogonal, there - * are two possible representations for group zero and we may need to - * preserve the current one to avoid changing the selected compression - * enable inadvertently. - */ - if (group == 8) - brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_2NDHALF); - else if (brw_inst_qtr_control(devinfo, inst) == BRW_COMPRESSION_2NDHALF) - brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE); } } @@ -507,12 +492,7 @@ brw_label_assembly(const struct brw_isa_info *isa, brw_create_label(&root_label, offset + brw_inst_jip(devinfo, inst) * to_bytes_scale, mem_ctx); } else if (brw_has_jip(devinfo, brw_inst_opcode(isa, inst))) { - int jip; - if (devinfo->ver >= 7) { - jip = brw_inst_jip(devinfo, inst); - } else { - jip = brw_inst_gfx6_jump_count(devinfo, inst); - } + int jip = brw_inst_jip(devinfo, inst); brw_create_label(&root_label, offset + jip * to_bytes_scale, mem_ctx); } @@ -775,23 +755,6 @@ brw_num_sources_from_inst(const struct brw_isa_info *isa, if (brw_inst_opcode(isa, inst) == BRW_OPCODE_MATH) { math_function = brw_inst_math_function(devinfo, inst); - } else if (devinfo->ver < 6 && - brw_inst_opcode(isa, inst) == BRW_OPCODE_SEND) { - if (brw_inst_sfid(devinfo, inst) == BRW_SFID_MATH) { - /* src1 must be a descriptor (including the information to determine - * that the SEND is doing an extended math operation), but src0 can - * actually be null since it serves as the source of the implicit GRF - * to MRF move. - * - * If we stop using that functionality, we'll have to revisit this. - */ - return 2; - } else { - /* Send instructions are allowed to have null sources since they use - * the base_mrf field to specify which message register source. - */ - return 0; - } } else { assert(desc->nsrc < 4); return desc->nsrc; diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h index b37c6e8ea76..7c702dcde82 100644 --- a/src/intel/compiler/brw_eu.h +++ b/src/intel/compiler/brw_eu.h @@ -288,34 +288,23 @@ brw_message_desc(const struct intel_device_info *devinfo, unsigned response_length, bool header_present) { - if (devinfo->ver >= 5) { - assert(msg_length % reg_unit(devinfo) == 0); - assert(response_length % reg_unit(devinfo) == 0); - return (SET_BITS(msg_length / reg_unit(devinfo), 28, 25) | - SET_BITS(response_length / reg_unit(devinfo), 24, 20) | - SET_BITS(header_present, 19, 19)); - } else { - return (SET_BITS(msg_length, 23, 20) | - SET_BITS(response_length, 19, 16)); - } + assert(msg_length % reg_unit(devinfo) == 0); + assert(response_length % reg_unit(devinfo) == 0); + return (SET_BITS(msg_length / reg_unit(devinfo), 28, 25) | + SET_BITS(response_length / reg_unit(devinfo), 24, 20) | + SET_BITS(header_present, 19, 19)); } static inline unsigned brw_message_desc_mlen(const struct intel_device_info *devinfo, uint32_t desc) { - if (devinfo->ver >= 5) - return GET_BITS(desc, 28, 25) * reg_unit(devinfo); - else - return GET_BITS(desc, 23, 20); + return GET_BITS(desc, 28, 25) * reg_unit(devinfo); } static inline unsigned brw_message_desc_rlen(const struct intel_device_info *devinfo, uint32_t desc) { - if (devinfo->ver >= 5) - return GET_BITS(desc, 24, 20) * reg_unit(devinfo); - else - return GET_BITS(desc, 19, 16); + return GET_BITS(desc, 24, 20) * reg_unit(devinfo); } static inline bool @@ -323,7 +312,6 @@ brw_message_desc_header_present(ASSERTED const struct intel_device_info *devinfo, uint32_t desc) { - assert(devinfo->ver >= 5); return GET_BITS(desc, 19, 19); } @@ -349,26 +337,16 @@ brw_urb_desc(const struct intel_device_info *devinfo, bool channel_mask_present, unsigned global_offset) { - if (devinfo->ver >= 8) { - return (SET_BITS(per_slot_offset_present, 17, 17) | - SET_BITS(channel_mask_present, 15, 15) | - SET_BITS(global_offset, 14, 4) | - SET_BITS(msg_type, 3, 0)); - } else if (devinfo->ver >= 7) { - assert(!channel_mask_present); - return (SET_BITS(per_slot_offset_present, 16, 16) | - SET_BITS(global_offset, 13, 3) | - SET_BITS(msg_type, 3, 0)); - } else { - unreachable("unhandled URB write generation"); - } + return (SET_BITS(per_slot_offset_present, 17, 17) | + SET_BITS(channel_mask_present, 15, 15) | + SET_BITS(global_offset, 14, 4) | + SET_BITS(msg_type, 3, 0)); } static inline uint32_t brw_urb_desc_msg_type(ASSERTED const struct intel_device_info *devinfo, uint32_t desc) { - assert(devinfo->ver >= 7); return GET_BITS(desc, 3, 0); } @@ -414,22 +392,10 @@ brw_sampler_desc(const struct intel_device_info *devinfo, * SIMD Mode[2] 29 This field is the upper bit of the 3-bit * SIMD Mode field. */ - if (devinfo->ver >= 8) - return desc | SET_BITS(msg_type, 16, 12) | - SET_BITS(simd_mode & 0x3, 18, 17) | - SET_BITS(simd_mode >> 2, 29, 29) | - SET_BITS(return_format, 30, 30); - if (devinfo->ver >= 7) - return (desc | SET_BITS(msg_type, 16, 12) | - SET_BITS(simd_mode, 18, 17)); - else if (devinfo->ver >= 5) - return (desc | SET_BITS(msg_type, 15, 12) | - SET_BITS(simd_mode, 17, 16)); - else if (devinfo->verx10 >= 45) - return desc | SET_BITS(msg_type, 15, 12); - else - return (desc | SET_BITS(return_format, 13, 12) | - SET_BITS(msg_type, 15, 14)); + return desc | SET_BITS(msg_type, 16, 12) | + SET_BITS(simd_mode & 0x3, 18, 17) | + SET_BITS(simd_mode >> 2, 29, 29) | + SET_BITS(return_format, 30, 30); } static inline unsigned @@ -452,36 +418,22 @@ brw_sampler_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc { if (devinfo->ver >= 20) return GET_BITS(desc, 31, 31) << 5 | GET_BITS(desc, 16, 12); - else if (devinfo->ver >= 7) - return GET_BITS(desc, 16, 12); - else if (devinfo->verx10 >= 45) - return GET_BITS(desc, 15, 12); else - return GET_BITS(desc, 15, 14); + return GET_BITS(desc, 16, 12); } static inline unsigned brw_sampler_desc_simd_mode(const struct intel_device_info *devinfo, uint32_t desc) { - assert(devinfo->ver >= 5); - if (devinfo->ver >= 8) - return GET_BITS(desc, 18, 17) | GET_BITS(desc, 29, 29) << 2; - else if (devinfo->ver >= 7) - return GET_BITS(desc, 18, 17); - else - return GET_BITS(desc, 17, 16); + return GET_BITS(desc, 18, 17) | GET_BITS(desc, 29, 29) << 2; } -static inline unsigned +static inline unsigned brw_sampler_desc_return_format(ASSERTED const struct intel_device_info *devinfo, uint32_t desc) { - assert(devinfo->verx10 == 40 || devinfo->ver >= 8); - if (devinfo->ver >= 8) - return GET_BITS(desc, 30, 30); - else - return GET_BITS(desc, 13, 12); + return GET_BITS(desc, 30, 30); } /** @@ -493,21 +445,9 @@ brw_dp_desc(const struct intel_device_info *devinfo, unsigned msg_type, unsigned msg_control) { - /* Prior to gfx6, things are too inconsistent; use the dp_read/write_desc - * helpers instead. - */ - assert(devinfo->ver >= 6); - const unsigned desc = SET_BITS(binding_table_index, 7, 0); - if (devinfo->ver >= 8) { - return (desc | SET_BITS(msg_control, 13, 8) | - SET_BITS(msg_type, 18, 14)); - } else if (devinfo->ver >= 7) { - return (desc | SET_BITS(msg_control, 13, 8) | - SET_BITS(msg_type, 17, 14)); - } else { - return (desc | SET_BITS(msg_control, 12, 8) | - SET_BITS(msg_type, 16, 13)); - } + return SET_BITS(binding_table_index, 7, 0) | + SET_BITS(msg_control, 13, 8) | + SET_BITS(msg_type, 18, 14); } static inline unsigned @@ -520,23 +460,13 @@ brw_dp_desc_binding_table_index(UNUSED const struct intel_device_info *devinfo, static inline unsigned brw_dp_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) { - assert(devinfo->ver >= 6); - if (devinfo->ver >= 8) - return GET_BITS(desc, 18, 14); - else if (devinfo->ver >= 7) - return GET_BITS(desc, 17, 14); - else - return GET_BITS(desc, 16, 13); + return GET_BITS(desc, 18, 14); } static inline unsigned brw_dp_desc_msg_control(const struct intel_device_info *devinfo, uint32_t desc) { - assert(devinfo->ver >= 6); - if (devinfo->ver >= 7) - return GET_BITS(desc, 13, 8); - else - return GET_BITS(desc, 12, 8); + return GET_BITS(desc, 13, 8); } /** @@ -550,42 +480,21 @@ brw_dp_read_desc(const struct intel_device_info *devinfo, unsigned msg_type, unsigned target_cache) { - if (devinfo->ver >= 6) - return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control); - else if (devinfo->verx10 >= 45) - return (SET_BITS(binding_table_index, 7, 0) | - SET_BITS(msg_control, 10, 8) | - SET_BITS(msg_type, 13, 11) | - SET_BITS(target_cache, 15, 14)); - else - return (SET_BITS(binding_table_index, 7, 0) | - SET_BITS(msg_control, 11, 8) | - SET_BITS(msg_type, 13, 12) | - SET_BITS(target_cache, 15, 14)); + return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control); } static inline unsigned brw_dp_read_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) { - if (devinfo->ver >= 6) - return brw_dp_desc_msg_type(devinfo, desc); - else if (devinfo->verx10 >= 45) - return GET_BITS(desc, 13, 11); - else - return GET_BITS(desc, 13, 12); + return brw_dp_desc_msg_type(devinfo, desc); } static inline unsigned brw_dp_read_desc_msg_control(const struct intel_device_info *devinfo, uint32_t desc) { - if (devinfo->ver >= 6) - return brw_dp_desc_msg_control(devinfo, desc); - else if (devinfo->verx10 >= 45) - return GET_BITS(desc, 10, 8); - else - return GET_BITS(desc, 11, 8); + return brw_dp_desc_msg_control(devinfo, desc); } /** @@ -599,47 +508,23 @@ brw_dp_write_desc(const struct intel_device_info *devinfo, unsigned msg_type, unsigned send_commit_msg) { - assert(devinfo->ver <= 6 || !send_commit_msg); - if (devinfo->ver >= 6) { - return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control) | - SET_BITS(send_commit_msg, 17, 17); - } else { - return (SET_BITS(binding_table_index, 7, 0) | - SET_BITS(msg_control, 11, 8) | - SET_BITS(msg_type, 14, 12) | - SET_BITS(send_commit_msg, 15, 15)); - } + assert(!send_commit_msg); + return brw_dp_desc(devinfo, binding_table_index, msg_type, msg_control) | + SET_BITS(send_commit_msg, 17, 17); } static inline unsigned brw_dp_write_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) { - if (devinfo->ver >= 6) - return brw_dp_desc_msg_type(devinfo, desc); - else - return GET_BITS(desc, 14, 12); + return brw_dp_desc_msg_type(devinfo, desc); } static inline unsigned brw_dp_write_desc_msg_control(const struct intel_device_info *devinfo, uint32_t desc) { - if (devinfo->ver >= 6) - return brw_dp_desc_msg_control(devinfo, desc); - else - return GET_BITS(desc, 11, 8); -} - -static inline bool -brw_dp_write_desc_write_commit(const struct intel_device_info *devinfo, - uint32_t desc) -{ - assert(devinfo->ver <= 6); - if (devinfo->ver >= 6) - return GET_BITS(desc, 17, 17); - else - return GET_BITS(desc, 15, 15); + return brw_dp_desc_msg_control(devinfo, desc); } /** @@ -651,7 +536,6 @@ brw_dp_surface_desc(const struct intel_device_info *devinfo, unsigned msg_type, unsigned msg_control) { - assert(devinfo->ver >= 7); /* We'll OR in the binding table index later */ return brw_dp_desc(devinfo, 0, msg_type, msg_control); } @@ -665,14 +549,10 @@ brw_dp_untyped_atomic_desc(const struct intel_device_info *devinfo, assert(exec_size <= 8 || exec_size == 16); unsigned msg_type; - if (devinfo->verx10 >= 75) { - if (exec_size > 0) { - msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP; - } else { - msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2; - } + if (exec_size > 0) { + msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP; } else { - msg_type = GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP; + msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2; } const unsigned msg_control = @@ -690,7 +570,6 @@ brw_dp_untyped_atomic_float_desc(const struct intel_device_info *devinfo, bool response_expected) { assert(exec_size <= 8 || exec_size == 16); - assert(devinfo->ver >= 9); assert(exec_size > 0); const unsigned msg_type = GFX9_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_FLOAT_OP; @@ -725,25 +604,9 @@ brw_dp_untyped_surface_rw_desc(const struct intel_device_info *devinfo, { assert(exec_size <= 8 || exec_size == 16); - unsigned msg_type; - if (write) { - if (devinfo->verx10 >= 75) { - msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE; - } else { - msg_type = GFX7_DATAPORT_DC_UNTYPED_SURFACE_WRITE; - } - } else { - /* Read */ - if (devinfo->verx10 >= 75) { - msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ; - } else { - msg_type = GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ; - } - } - - /* SIMD4x2 is only valid for read messages on IVB; use SIMD8 instead */ - if (write && devinfo->verx10 == 70 && exec_size == 0) - exec_size = 8; + const unsigned msg_type = + write ? HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE : + HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ; /* See also MDC_SM3 in the SKL PRM Vol 2d. */ const unsigned simd_mode = exec_size == 0 ? 0 : /* SIMD4x2 */ @@ -779,7 +642,6 @@ brw_dp_byte_scattered_rw_desc(const struct intel_device_info *devinfo, { assert(exec_size <= 8 || exec_size == 16); - assert(devinfo->verx10 >= 75); const unsigned msg_type = write ? HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE : HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ; @@ -799,22 +661,9 @@ brw_dp_dword_scattered_rw_desc(const struct intel_device_info *devinfo, { assert(exec_size == 8 || exec_size == 16); - unsigned msg_type; - if (write) { - if (devinfo->ver >= 6) { - msg_type = GFX6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE; - } else { - msg_type = BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE; - } - } else { - if (devinfo->ver >= 7) { - msg_type = GFX7_DATAPORT_DC_DWORD_SCATTERED_READ; - } else if (devinfo->verx10 >= 45) { - msg_type = G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ; - } else { - msg_type = BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ; - } - } + const unsigned msg_type = + write ? GFX6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE : + GFX7_DATAPORT_DC_DWORD_SCATTERED_READ; const unsigned msg_control = SET_BITS(1, 1, 1) | /* Legacy SIMD Mode */ @@ -850,7 +699,6 @@ brw_dp_a64_untyped_surface_rw_desc(const struct intel_device_info *devinfo, bool write) { assert(exec_size <= 8 || exec_size == 16); - assert(devinfo->ver >= 8); unsigned msg_type = write ? GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE : @@ -913,7 +761,6 @@ brw_dp_a64_byte_scattered_rw_desc(const struct intel_device_info *devinfo, bool write) { assert(exec_size <= 8 || exec_size == 16); - assert(devinfo->ver >= 8); unsigned msg_type = write ? GFX8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE : @@ -936,7 +783,6 @@ brw_dp_a64_untyped_atomic_desc(const struct intel_device_info *devinfo, bool response_expected) { assert(exec_size == 8); - assert(devinfo->ver >= 8); assert(bit_size == 16 || bit_size == 32 || bit_size == 64); assert(devinfo->ver >= 12 || bit_size >= 32); @@ -961,7 +807,6 @@ brw_dp_a64_untyped_atomic_float_desc(const struct intel_device_info *devinfo, bool response_expected) { assert(exec_size == 8); - assert(devinfo->ver >= 9); assert(bit_size == 16 || bit_size == 32); assert(devinfo->ver >= 12 || bit_size == 32); @@ -988,18 +833,9 @@ brw_dp_typed_atomic_desc(const struct intel_device_info *devinfo, assert(exec_size > 0 || exec_group == 0); assert(exec_group % 8 == 0); - unsigned msg_type; - if (devinfo->verx10 >= 75) { - if (exec_size == 0) { - msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2; - } else { - msg_type = HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP; - } - } else { - /* SIMD4x2 typed surface R/W messages only exist on HSW+ */ - assert(exec_size > 0); - msg_type = GFX7_DATAPORT_RC_TYPED_ATOMIC_OP; - } + const unsigned msg_type = + exec_size == 0 ? HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 : + HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP; const bool high_sample_mask = (exec_group / 8) % 2 == 1; @@ -1024,40 +860,17 @@ brw_dp_typed_surface_rw_desc(const struct intel_device_info *devinfo, /* Typed surface reads and writes don't support SIMD16 */ assert(exec_size <= 8); - unsigned msg_type; - if (write) { - if (devinfo->verx10 >= 75) { - msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE; - } else { - msg_type = GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE; - } - } else { - if (devinfo->verx10 >= 75) { - msg_type = HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ; - } else { - msg_type = GFX7_DATAPORT_RC_TYPED_SURFACE_READ; - } - } + const unsigned msg_type = + write ? HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE : + HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ; /* See also MDC_SG3 in the SKL PRM Vol 2d. */ - unsigned msg_control; - if (devinfo->verx10 >= 75) { - /* See also MDC_SG3 in the SKL PRM Vol 2d. */ - const unsigned slot_group = exec_size == 0 ? 0 : /* SIMD4x2 */ - 1 + ((exec_group / 8) % 2); + const unsigned slot_group = exec_size == 0 ? 0 : /* SIMD4x2 */ + 1 + ((exec_group / 8) % 2); - msg_control = - SET_BITS(brw_mdc_cmask(num_channels), 3, 0) | - SET_BITS(slot_group, 5, 4); - } else { - /* SIMD4x2 typed surface R/W messages only exist on HSW+ */ - assert(exec_size > 0); - const unsigned slot_group = ((exec_group / 8) % 2); - - msg_control = - SET_BITS(brw_mdc_cmask(num_channels), 3, 0) | - SET_BITS(slot_group, 5, 5); - } + const unsigned msg_control = + SET_BITS(brw_mdc_cmask(num_channels), 3, 0) | + SET_BITS(slot_group, 5, 4); return brw_dp_surface_desc(devinfo, msg_type, msg_control); } @@ -1068,18 +881,9 @@ brw_fb_desc(const struct intel_device_info *devinfo, unsigned msg_type, unsigned msg_control) { - /* Prior to gen6, things are too inconsistent; use the fb_(read|write)_desc - * helpers instead. - */ - assert(devinfo->ver >= 6); - const unsigned desc = SET_BITS(binding_table_index, 7, 0); - if (devinfo->ver >= 7) { - return (desc | SET_BITS(msg_control, 13, 8) | - SET_BITS(msg_type, 17, 14)); - } else { - return (desc | SET_BITS(msg_control, 12, 8) | - SET_BITS(msg_type, 16, 13)); - } + return SET_BITS(binding_table_index, 7, 0) | + SET_BITS(msg_control, 13, 8) | + SET_BITS(msg_type, 17, 14); } static inline unsigned @@ -1092,21 +896,13 @@ brw_fb_desc_binding_table_index(UNUSED const struct intel_device_info *devinfo, static inline uint32_t brw_fb_desc_msg_control(const struct intel_device_info *devinfo, uint32_t desc) { - assert(devinfo->ver >= 6); - if (devinfo->ver >= 7) - return GET_BITS(desc, 13, 8); - else - return GET_BITS(desc, 12, 8); + return GET_BITS(desc, 13, 8); } static inline unsigned brw_fb_desc_msg_type(const struct intel_device_info *devinfo, uint32_t desc) { - assert(devinfo->ver >= 6); - if (devinfo->ver >= 7) - return GET_BITS(desc, 17, 14); - else - return GET_BITS(desc, 16, 13); + return GET_BITS(desc, 17, 14); } static inline uint32_t @@ -1116,7 +912,6 @@ brw_fb_read_desc(const struct intel_device_info *devinfo, unsigned exec_size, bool per_sample) { - assert(devinfo->ver >= 9); assert(exec_size == 8 || exec_size == 16); return brw_fb_desc(devinfo, binding_table_index, @@ -1132,64 +927,20 @@ brw_fb_write_desc(const struct intel_device_info *devinfo, bool last_render_target, bool coarse_write) { - const unsigned msg_type = - devinfo->ver >= 6 ? - GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE : - BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE; + const unsigned msg_type = GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE; assert(devinfo->ver >= 10 || !coarse_write); - if (devinfo->ver >= 6) { - return brw_fb_desc(devinfo, binding_table_index, msg_type, msg_control) | - SET_BITS(last_render_target, 12, 12) | - SET_BITS(coarse_write, 18, 18); - } else { - return (SET_BITS(binding_table_index, 7, 0) | - SET_BITS(msg_control, 11, 8) | - SET_BITS(last_render_target, 11, 11) | - SET_BITS(msg_type, 14, 12)); - } -} - -static inline unsigned -brw_fb_write_desc_msg_type(const struct intel_device_info *devinfo, - uint32_t desc) -{ - if (devinfo->ver >= 6) - return brw_fb_desc_msg_type(devinfo, desc); - else - return GET_BITS(desc, 14, 12); -} - -static inline unsigned -brw_fb_write_desc_msg_control(const struct intel_device_info *devinfo, - uint32_t desc) -{ - if (devinfo->ver >= 6) - return brw_fb_desc_msg_control(devinfo, desc); - else - return GET_BITS(desc, 11, 8); + return brw_fb_desc(devinfo, binding_table_index, msg_type, msg_control) | + SET_BITS(last_render_target, 12, 12) | + SET_BITS(coarse_write, 18, 18); } static inline bool brw_fb_write_desc_last_render_target(const struct intel_device_info *devinfo, uint32_t desc) { - if (devinfo->ver >= 6) - return GET_BITS(desc, 12, 12); - else - return GET_BITS(desc, 11, 11); -} - -static inline bool -brw_fb_write_desc_write_commit(const struct intel_device_info *devinfo, - uint32_t desc) -{ - assert(devinfo->ver <= 6); - if (devinfo->ver >= 6) - return GET_BITS(desc, 17, 17); - else - return GET_BITS(desc, 15, 15); + return GET_BITS(desc, 12, 12); } static inline bool @@ -1806,17 +1557,7 @@ static inline unsigned brw_jump_scale(const struct intel_device_info *devinfo) { /* Broadwell measures jump targets in bytes. */ - if (devinfo->ver >= 8) - return 16; - - /* Ironlake and later measure jump targets in 64-bit data chunks (in order - * (to support compaction), so each 128-bit instruction requires 2 chunks. - */ - if (devinfo->ver >= 5) - return 2; - - /* Gfx4 simply uses the number of 128-bit instructions. */ - return 1; + return 16; } void brw_barrier(struct brw_codegen *p, struct brw_reg src);