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pan/bi: Handle vector moves
And fix the bad assertion that let this slip. Like combines, nir_op_vec can be vector, and we need to lower this ourselves. Thankfully, the lowering is simple. Fixes dEQP-GLES2.functional.shaders.loops.for_uniform_iterations.nested_tricky_dataflow_1_* Fixes:b2c6cf2b6d("pan/bi: Eliminate writemasks in the IR") Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081> (cherry picked from commita204eac759)
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parent
21f7264ff4
commit
d611e2fd71
2 changed files with 12 additions and 4 deletions
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@ -463,7 +463,7 @@
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"description": "pan/bi: Handle vector moves",
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"nominated": true,
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"nomination_type": 1,
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"resolution": 0,
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"resolution": 1,
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"master_sha": null,
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"because_sha": "b2c6cf2b6db11eb2293f59b42dfeb3d7481477b0"
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},
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@ -751,9 +751,8 @@ emit_alu(bi_context *ctx, nir_alu_instr *instr)
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assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
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unsigned comps = nir_dest_num_components(instr->dest.dest);
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if (alu.type != BI_COMBINE)
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assert(comps <= MAX2(1, 32 / comps));
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bool vector = comps > MAX2(1, 32 / nir_dest_bit_size(instr->dest.dest));
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assert(!vector || alu.type == BI_COMBINE || alu.type == BI_MOV);
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if (!instr->dest.dest.is_ssa) {
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for (unsigned i = 0; i < comps; ++i)
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@ -910,6 +909,15 @@ emit_alu(bi_context *ctx, nir_alu_instr *instr)
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break;
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}
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if (alu.type == BI_MOV && vector) {
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alu.type = BI_COMBINE;
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for (unsigned i = 0; i < comps; ++i) {
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alu.src[i] = alu.src[0];
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alu.swizzle[i][0] = instr->src[0].swizzle[i];
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}
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}
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if (alu.type == BI_CSEL) {
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/* Default to csel3 */
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alu.cond = BI_COND_NE;
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