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radv/amdgpu: fix CS padding for non-GFX/COMPUTE queues

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I forgot that SDMA and VIDEO existed somehow.

Fixes: d690f293c6 ("radv/winsys: pad gfx and compute IBs with only one NOP")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30769>
This commit is contained in:
Samuel Pitoiset 2024-08-21 19:20:43 +02:00 • committed by Marge Bot
parent c5156257d9
commit d5efbc7f1c
1 changed files with 33 additions and 29 deletions
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62
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
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@ -429,22 +429,40 @@ radv_amdgpu_winsys_cs_pad(struct radeon_cmdbuf *_cs, unsigned leave_dw_space)
const uint32_t pad_dw_mask = cs->ws->info.ip[ip_type].ib_pad_dw_mask; const uint32_t pad_dw_mask = cs->ws->info.ip[ip_type].ib_pad_dw_mask;
const uint32_t unaligned_dw = (cs->base.cdw + leave_dw_space) & pad_dw_mask; const uint32_t unaligned_dw = (cs->base.cdw + leave_dw_space) & pad_dw_mask;
assert(ip_type == AMD_IP_GFX || ip_type == AMD_IP_COMPUTE); if (ip_type == AMD_IP_GFX || ip_type == AMD_IP_COMPUTE) {
if (unaligned_dw) {
const int remaining = pad_dw_mask + 1 - unaligned_dw;
if (unaligned_dw) { /* Only pad by 1 dword with the type-2 NOP if necessary. */
const int remaining = pad_dw_mask + 1 - unaligned_dw; if (remaining == 1 && cs->ws->info.gfx_ib_pad_with_type2) {
radeon_emit_unchecked(&cs->base, PKT2_NOP_PAD);
} else {
/* Pad with a single NOP packet to minimize CP overhead because NOP is a variable-sized
* packet. The size of the packet body after the header is always count + 1.
* If count == -1, there is no packet body. NOP is the only packet that can have
* count == -1, which is the definition of PKT3_NOP_PAD (count == 0x3fff means -1).
*/
radeon_emit_unchecked(&cs->base, PKT3(PKT3_NOP, remaining - 2, 0));
cs->base.cdw += remaining - 1;
}
}
} else {
/* Pad the CS with NOP packets. */
bool pad = true;
/* Only pad by 1 dword with the type-2 NOP if necessary. */ /* Don't pad on VCN encode/unified as no NOPs */
if (remaining == 1 && cs->ws->info.gfx_ib_pad_with_type2) { if (ip_type == AMDGPU_HW_IP_VCN_ENC)
radeon_emit_unchecked(&cs->base, PKT2_NOP_PAD); pad = false;
} else {
/* Pad with a single NOP packet to minimize CP overhead because NOP is a variable-sized /* Don't add padding to 0 length UVD due to kernel */
* packet. The size of the packet body after the header is always count + 1. if (ip_type == AMDGPU_HW_IP_UVD && cs->base.cdw == 0)
* If count == -1, there is no packet body. NOP is the only packet that can have pad = false;
* count == -1, which is the definition of PKT3_NOP_PAD (count == 0x3fff means -1).
*/ if (pad) {
radeon_emit_unchecked(&cs->base, PKT3(PKT3_NOP, remaining - 2, 0)); const uint32_t nop_packet = get_nop_packet(cs);
cs->base.cdw += remaining - 1;
while (!cs->base.cdw || (cs->base.cdw & pad_dw_mask))
radeon_emit_unchecked(&cs->base, nop_packet);
} }
} }
@ -455,7 +473,6 @@ static VkResult
radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs) radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
{ {
struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs); struct radv_amdgpu_cs *cs = radv_amdgpu_cs(_cs);
enum amd_ip_type ip_type = cs->hw_ip;
assert(cs->base.cdw <= cs->base.reserved_dw); assert(cs->base.cdw <= cs->base.reserved_dw);
@ -472,20 +489,7 @@ radv_amdgpu_cs_finalize(struct radeon_cmdbuf *_cs)
*cs->ib_size_ptr |= cs->base.cdw; *cs->ib_size_ptr |= cs->base.cdw;
} else { } else {
/* Pad the CS with NOP packets. */ radv_amdgpu_winsys_cs_pad(_cs, 0);
bool pad = true;
/* Don't pad on VCN encode/unified as no NOPs */
if (ip_type == AMDGPU_HW_IP_VCN_ENC)
pad = false;
/* Don't add padding to 0 length UVD due to kernel */
if (ip_type == AMDGPU_HW_IP_UVD && cs->base.cdw == 0)
pad = false;
if (pad) {
radv_amdgpu_winsys_cs_pad(_cs, 0);
}
} }
/* Append the current (last) IB to the array of IB buffers. */ /* Append the current (last) IB to the array of IB buffers. */