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Hardware accelerated depth clear
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parent
94987beb2c
commit
d586540eaf
5 changed files with 62 additions and 16 deletions
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@ -376,8 +376,10 @@ void r300InitCmdBuf(r300ContextPtr r300)
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r300->hw.unk4E88.cmd[0] = cmducs(0x4E88, 1);
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ALLOC_STATE( zc, always, R300_ZC_CMDSIZE, "zc", 0 );
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r300->hw.zc.cmd[R300_ZC_CMD_0] = cmducs(R300_RB3D_ZCNTL_0, 2);
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ALLOC_STATE( unk4F08, always, 6, "unk4F08", 0 );
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r300->hw.unk4F08.cmd[0] = cmducs(0x4F08, 5);
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ALLOC_STATE( unk4F08, always, 2, "unk4F08", 0 );
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r300->hw.unk4F08.cmd[0] = cmducs(0x4F08, 1);
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ALLOC_STATE( unk4F10, always, 5, "unk4F10", 0 );
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r300->hw.unk4F10.cmd[0] = cmducs(0x4F10, 4);
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ALLOC_STATE( zb, always, R300_ZB_CMDSIZE, "zb", 0 );
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r300->hw.zb.cmd[R300_ZB_CMD_0] = cmducs(R300_RB3D_DEPTHOFFSET, 2);
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ALLOC_STATE( unk4F28, always, 2, "unk4F28", 0 );
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@ -451,6 +453,7 @@ void r300InitCmdBuf(r300ContextPtr r300)
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insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4E88);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.zc);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F08);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F10);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.zb);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F28);
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insert_at_tail(&r300->hw.atomlist, &r300->hw.unk4F30);
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@ -269,6 +269,7 @@ struct r300_hw_state {
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struct r300_state_atom unk4E88; /* (4E88) */
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struct r300_state_atom zc; /* z control (4F00) */
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struct r300_state_atom unk4F08; /* (4F08) */
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struct r300_state_atom unk4F10; /* (4F10) */
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struct r300_state_atom zb; /* z buffer (4F20) */
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struct r300_state_atom unk4F28; /* (4F28) */
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struct r300_state_atom unk4F30; /* (4F30) */
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@ -55,7 +55,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#include "vblank.h"
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static void r300ClearBuffer(r300ContextPtr r300, int buffer)
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#define CLEARBUFFER_COLOR 0x1
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#define CLEARBUFFER_DEPTH 0x2
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static void r300ClearBuffer(r300ContextPtr r300, int flags, int buffer)
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{
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GLcontext* ctx = r300->radeon.glCtx;
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__DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
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@ -107,7 +110,10 @@ static void r300ClearBuffer(r300ContextPtr r300, int buffer)
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r300->hw.rr.cmd[1] = 0x00004000;
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R300_STATECHANGE(r300, cmk);
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r300->hw.cmk.cmd[R300_CMK_COLORMASK] = 0xF;
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if (flags & CLEARBUFFER_COLOR)
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r300->hw.cmk.cmd[R300_CMK_COLORMASK] = 0xF;
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else
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r300->hw.cmk.cmd[R300_CMK_COLORMASK] = 0;
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R300_STATECHANGE(r300, fp);
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r300->hw.fp.cmd[R300_FP_CNTL0] = 0; /* 1 pass, no textures */
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@ -157,6 +163,24 @@ static void r300ClearBuffer(r300ContextPtr r300, int buffer)
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r300->hw.vpi.cmd[7] = VP_ZERO();
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r300->hw.vpi.cmd[8] = 0;
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R300_STATECHANGE(r300, zc);
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if (flags & CLEARBUFFER_DEPTH) {
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r300->hw.zc.cmd[R300_ZC_CNTL_0] = 0x6; // test and write
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r300->hw.zc.cmd[R300_ZC_CNTL_1] = R300_RB3D_Z_TEST_ALWAYS;
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/*
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R300_STATECHANGE(r300, zb);
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r300->hw.zb.cmd[R300_ZB_OFFSET] =
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1024*4*300 +
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r300->radeon.radeonScreen->frontOffset +
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r300->radeon.radeonScreen->fbLocation;
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r300->hw.zb.cmd[R300_ZB_PITCH] =
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r300->radeon.radeonScreen->depthPitch;
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*/
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} else {
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r300->hw.zc.cmd[R300_ZC_CNTL_0] = 0; // disable
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r300->hw.zc.cmd[R300_ZC_CNTL_1] = 0;
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}
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/* Make sure we have enough space */
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r300EnsureCmdBufSpace(r300, r300->hw.max_state_size + 9, __FUNCTION__);
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@ -167,7 +191,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int buffer)
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cmd[0].packet3.packet = R300_CMD_PACKET3_CLEAR;
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cmd[1].u = r300PackFloat32(dPriv->w / 2.0);
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cmd[2].u = r300PackFloat32(dPriv->h / 2.0);
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cmd[3].u = r300PackFloat32(0.0);
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cmd[3].u = r300PackFloat32(ctx->Depth.Clear);
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cmd[4].u = r300PackFloat32(1.0);
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cmd[5].u = r300PackFloat32(ctx->Color.ClearColor[0]);
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cmd[6].u = r300PackFloat32(ctx->Color.ClearColor[1]);
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@ -185,6 +209,7 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask, GLboolean all,
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r300ContextPtr r300 = R300_CONTEXT(ctx);
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__DRIdrawablePrivate *dPriv = r300->radeon.dri.drawable;
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int flags = 0;
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int bits = 0;
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int swapped;
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if (RADEON_DEBUG & DEBUG_IOCTL)
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@ -208,6 +233,12 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask, GLboolean all,
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mask &= ~DD_BACK_LEFT_BIT;
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}
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if (mask & DD_DEPTH_BIT) {
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if (ctx->Depth.Mask)
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bits |= CLEARBUFFER_DEPTH;
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mask &= ~DD_DEPTH_BIT;
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}
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if (mask) {
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if (RADEON_DEBUG & DEBUG_FALLBACKS)
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fprintf(stderr, "%s: swrast clear, mask: %x\n",
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@ -217,11 +248,18 @@ static void r300Clear(GLcontext * ctx, GLbitfield mask, GLboolean all,
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swapped = r300->radeon.doPageFlip && (r300->radeon.sarea->pfCurrentPage == 1);
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if (flags & DD_FRONT_LEFT_BIT)
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r300ClearBuffer(r300, swapped);
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if (flags & DD_FRONT_LEFT_BIT) {
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r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, swapped);
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bits = 0;
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}
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if (flags & DD_BACK_LEFT_BIT)
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r300ClearBuffer(r300, swapped ^ 1);
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if (flags & DD_BACK_LEFT_BIT) {
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r300ClearBuffer(r300, bits | CLEARBUFFER_COLOR, swapped ^ 1);
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bits = 0;
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}
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if (bits)
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r300ClearBuffer(r300, bits, 0);
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/* Recalculate the hardware state. This could be done more efficiently,
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* but do keep it like this for now.
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@ -295,10 +295,11 @@ void r300ResetHwState(r300ContextPtr r300)
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r300->hw.zc.cmd[R300_ZC_CNTL_1] = 0;
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r300->hw.unk4F08.cmd[1] = 0x00FFFF00;
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r300->hw.unk4F08.cmd[2] = 0x00000002;
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r300->hw.unk4F08.cmd[3] = 0x00000000;
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r300->hw.unk4F08.cmd[4] = 0x00000003;
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r300->hw.unk4F08.cmd[5] = 0x00000000;
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r300->hw.unk4F10.cmd[1] = 0x00000002; // depthbuffer format?
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r300->hw.unk4F10.cmd[2] = 0x00000000;
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r300->hw.unk4F10.cmd[3] = 0x00000003;
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r300->hw.unk4F10.cmd[4] = 0x00000000;
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r300->hw.zb.cmd[R300_ZB_OFFSET] =
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r300->radeon.radeonScreen->depthOffset +
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@ -257,18 +257,21 @@ do { \
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#include "depthtmp.h"
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/* 24 bit depth, 8 bit stencil depthbuffer functions
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*
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* Careful: It looks like the R300 uses ZZZS byte order while the R200
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* uses SZZZ for 24 bit depth, 8 bit stencil mode.
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*/
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#define WRITE_DEPTH( _x, _y, d ) \
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do { \
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GLuint offset = (_x + xo + (_y + yo)*pitch)*4; \
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GLuint tmp = *(GLuint *)(buf + offset); \
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tmp &= 0xff000000; \
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tmp |= ((d) & 0x00ffffff); \
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tmp &= 0x000000ff; \
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tmp |= ((d << 8) & 0xffffff00); \
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*(GLuint *)(buf + offset) = tmp; \
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} while (0)
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#define READ_DEPTH( d, _x, _y ) \
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d = *(GLuint *)(buf + (_x + xo + (_y + yo)*pitch)*4) & 0x00ffffff;
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d = (*(GLuint *)(buf + (_x + xo + (_y + yo)*pitch)*4) & 0xffffff00) >> 8;
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#define TAG(x) radeon##x##_24_8_LINEAR
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#include "depthtmp.h"
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