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radeonsi: add load_polygon_stipple_buffer_amd instead of using si_shader_args

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We will lower polygon stipple before we have si_shader_args, so we need
an intrinsic to get the buffer descriptor.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32910>
This commit is contained in:
Marek Olšák 2024-12-26 07:01:44 -05:00 • committed by Marge Bot
parent cd3079a1ea
commit d580313929
4 changed files with 14 additions and 7 deletions
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1
src/compiler/nir/nir_divergence_analysis.c
View file

@ -345,6 +345,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
case nir_intrinsic_optimization_barrier_sgpr_amd:
case nir_intrinsic_load_fbfetch_image_fmask_desc_amd:
case nir_intrinsic_load_fbfetch_image_desc_amd:
case nir_intrinsic_load_polygon_stipple_buffer_amd:
case nir_intrinsic_load_printf_buffer_address:
case nir_intrinsic_load_printf_buffer_size:
case nir_intrinsic_load_printf_base_identifier:

3
src/compiler/nir/nir_intrinsics.py
View file

@ -1821,6 +1821,9 @@ system_value("num_vertices_per_primitive_amd", 1)
# BASE = buffer index
intrinsic("load_streamout_buffer_amd", dest_comp=4, indices=[BASE], bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER])
# Polygon stipple buffer descriptor
system_value("polygon_stipple_buffer_amd", 4)
# An ID for each workgroup ordered by primitve sequence
system_value("ordered_id_amd", 1)

3
src/gallium/drivers/radeonsi/si_nir_lower_abi.c
View file

@ -612,6 +612,9 @@ static bool lower_intrinsic(nir_builder *b, nir_instr *instr, struct lower_abi_s
STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0 % 2 == 0);
replacement = si_nir_load_internal_binding(b, args, SI_PS_IMAGE_COLORBUF0, 8);
break;
case nir_intrinsic_load_polygon_stipple_buffer_amd:
replacement = si_nir_load_internal_binding(b, args, SI_PS_CONST_POLY_STIPPLE, 4);
break;
default:
return false;
}

14
src/gallium/drivers/radeonsi/si_shader.c
View file

@ -2112,7 +2112,7 @@ static bool si_nir_lower_ps_color_input(nir_shader *nir, const union si_shader_k
colors) || progress;
}
static void si_nir_emit_polygon_stipple(nir_shader *nir, struct si_shader_args *args)
static bool si_nir_emit_polygon_stipple(nir_shader *nir)
{
nir_function_impl *impl = nir_shader_get_entrypoint(nir);
@ -2120,8 +2120,7 @@ static void si_nir_emit_polygon_stipple(nir_shader *nir, struct si_shader_args *
nir_builder *b = &builder;
/* Load the buffer descriptor. */
nir_def *desc =
si_nir_load_internal_binding(b, args, SI_PS_CONST_POLY_STIPPLE, 4);
nir_def *desc = nir_load_polygon_stipple_buffer_amd(b);
/* Use the fixed-point gl_FragCoord input.
* Since the stipple pattern is 32x32 and it repeats, just get 5 bits
@ -2137,6 +2136,9 @@ static void si_nir_emit_polygon_stipple(nir_shader *nir, struct si_shader_args *
nir_def *pass = nir_i2b(b, bit);
nir_discard_if(b, nir_inot(b, pass));
nir_metadata_preserve(impl, nir_metadata_control_flow);
return true;
}
bool si_should_clear_lds(struct si_screen *sscreen, const struct nir_shader *shader)
@ -2462,10 +2464,8 @@ static struct nir_shader *si_get_nir_shader(struct si_shader *shader, struct si_
NIR_PASS(progress, nir, ac_nir_lower_ps_late, &late_options);
if (key->ps.part.prolog.poly_stipple) {
NIR_PASS_V(nir, si_nir_emit_polygon_stipple, args);
progress = true;
}
if (key->ps.part.prolog.poly_stipple)
NIR_PASS(progress, nir, si_nir_emit_polygon_stipple);
}
assert(shader->wave_size == 32 || shader->wave_size == 64);