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radv,aco: Lower uclz in NIR.

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Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18951>
This commit is contained in:
Georg Lehmann 2022-10-04 15:44:16 +02:00
parent 7505be3497
commit d57f5c9cac
2 changed files with 1 additions and 13 deletions
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13
src/amd/compiler/aco_instruction_selection.cpp
View file

@ -1838,19 +1838,6 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr)
}
break;
}
case nir_op_uclz: {
Temp src = get_alu_src(ctx, instr->src[0]);
if (src.regClass() == s1) {
Temp msb_rev = bld.sop1(aco_opcode::s_flbit_i32_b32, bld.def(s1), src);
bld.sop2(aco_opcode::s_min_u32, Definition(dst), Operand::c32(32u), msb_rev);
} else if (src.regClass() == v1) {
Temp msb_rev = bld.vop1(aco_opcode::v_ffbh_u32, bld.def(v1), src);
bld.vop2(aco_opcode::v_min_u32, Definition(dst), Operand::c32(32u), msb_rev);
} else {
isel_err(&instr->instr, "Unimplemented NIR instr bit size");
}
break;
}
case nir_op_bitfield_reverse: {
if (dst.regClass() == s1) {
bld.sop1(aco_opcode::s_brev_b32, Definition(dst), get_alu_src(ctx, instr->src[0]));

1
src/amd/vulkan/radv_shader.c
View file

@ -91,6 +91,7 @@ get_nir_options_for_stage(struct radv_physical_device *device, gl_shader_stage s
.lower_iadd_sat = device->rad_info.gfx_level <= GFX8,
.lower_hadd = true,
.lower_mul_32x16 = true,
.lower_uclz = true,
.has_fsub = true,
.has_isub = true,
.has_sdot_4x8 = device->rad_info.has_accelerated_dot_product,