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radeonsi/vcn: Set H264/HEVC chroma sample location in bitstream
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25078>
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8e76b8fb35
commit
d57241d290
4 changed files with 33 additions and 3 deletions
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@ -546,6 +546,7 @@ typedef struct rvcn_enc_vui_info_s
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uint32_t timing_info_present_flag : 1;
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uint32_t video_signal_type_present_flag : 1;
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uint32_t colour_description_present_flag : 1;
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uint32_t chroma_loc_info_present_flag : 1;
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} flags;
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uint32_t aspect_ratio_idc;
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uint32_t sar_width;
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@ -557,6 +558,8 @@ typedef struct rvcn_enc_vui_info_s
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uint32_t colour_primaries;
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uint32_t transfer_characteristics;
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uint32_t matrix_coefficients;
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uint32_t chroma_sample_loc_type_top_field;
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uint32_t chroma_sample_loc_type_bottom_field;
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}rvcn_enc_vui_info;
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typedef struct rvcn_enc_input_format_s
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@ -173,6 +173,8 @@ static void radeon_vcn_enc_h264_get_vui_param(struct radeon_encoder *enc,
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pic->seq.vui_flags.video_signal_type_present_flag;
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enc->enc_pic.vui_info.flags.colour_description_present_flag =
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pic->seq.vui_flags.colour_description_present_flag;
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enc->enc_pic.vui_info.flags.chroma_loc_info_present_flag =
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pic->seq.vui_flags.chroma_loc_info_present_flag;
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enc->enc_pic.vui_info.aspect_ratio_idc = pic->seq.aspect_ratio_idc;
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enc->enc_pic.vui_info.sar_width = pic->seq.sar_width;
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enc->enc_pic.vui_info.sar_height = pic->seq.sar_height;
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@ -183,6 +185,10 @@ static void radeon_vcn_enc_h264_get_vui_param(struct radeon_encoder *enc,
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enc->enc_pic.vui_info.colour_primaries = pic->seq.colour_primaries;
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enc->enc_pic.vui_info.transfer_characteristics = pic->seq.transfer_characteristics;
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enc->enc_pic.vui_info.matrix_coefficients = pic->seq.matrix_coefficients;
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enc->enc_pic.vui_info.chroma_sample_loc_type_top_field =
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pic->seq.chroma_sample_loc_type_top_field;
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enc->enc_pic.vui_info.chroma_sample_loc_type_bottom_field =
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pic->seq.chroma_sample_loc_type_bottom_field;
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}
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/* only checking the first slice to get num of mbs in slice to
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@ -401,6 +407,8 @@ static void radeon_vcn_enc_hevc_get_vui_param(struct radeon_encoder *enc,
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pic->seq.vui_flags.video_signal_type_present_flag;
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enc->enc_pic.vui_info.flags.colour_description_present_flag =
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pic->seq.vui_flags.colour_description_present_flag;
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enc->enc_pic.vui_info.flags.chroma_loc_info_present_flag =
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pic->seq.vui_flags.chroma_loc_info_present_flag;
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enc->enc_pic.vui_info.aspect_ratio_idc = pic->seq.aspect_ratio_idc;
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enc->enc_pic.vui_info.sar_width = pic->seq.sar_width;
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enc->enc_pic.vui_info.sar_height = pic->seq.sar_height;
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@ -411,6 +419,10 @@ static void radeon_vcn_enc_hevc_get_vui_param(struct radeon_encoder *enc,
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enc->enc_pic.vui_info.colour_primaries = pic->seq.colour_primaries;
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enc->enc_pic.vui_info.transfer_characteristics = pic->seq.transfer_characteristics;
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enc->enc_pic.vui_info.matrix_coefficients = pic->seq.matrix_coefficients;
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enc->enc_pic.vui_info.chroma_sample_loc_type_top_field =
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pic->seq.chroma_sample_loc_type_top_field;
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enc->enc_pic.vui_info.chroma_sample_loc_type_bottom_field =
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pic->seq.chroma_sample_loc_type_bottom_field;
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}
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/* only checking the first slice to get num of ctbs in slice to
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@ -316,7 +316,12 @@ static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
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radeon_enc_code_fixed_bits(enc, pic->vui_info.matrix_coefficients, 8);
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}
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}
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radeon_enc_code_fixed_bits(enc, 0x0, 1); /* chroma loc info present flag */
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/* chroma loc info present flag */
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radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.chroma_loc_info_present_flag, 1);
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if (pic->vui_info.flags.chroma_loc_info_present_flag) {
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radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_top_field);
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radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_bottom_field);
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}
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/* timing info present flag */
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radeon_enc_code_fixed_bits(enc, (pic->vui_info.flags.timing_info_present_flag), 1);
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if (pic->vui_info.flags.timing_info_present_flag) {
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@ -456,7 +461,12 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
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radeon_enc_code_fixed_bits(enc, pic->vui_info.matrix_coefficients, 8);
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}
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}
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radeon_enc_code_fixed_bits(enc, 0x0, 1); /* chroma loc info present flag */
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/* chroma loc info present flag */
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radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.chroma_loc_info_present_flag, 1);
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if (pic->vui_info.flags.chroma_loc_info_present_flag) {
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radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_top_field);
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radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_bottom_field);
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}
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radeon_enc_code_fixed_bits(enc, 0x0, 1); /* neutral chroma indication flag */
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radeon_enc_code_fixed_bits(enc, 0x0, 1); /* field seq flag */
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radeon_enc_code_fixed_bits(enc, 0x0, 1); /* frame field info present flag */
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@ -348,7 +348,12 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
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radeon_enc_code_fixed_bits(enc, pic->vui_info.matrix_coefficients, 8);
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}
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}
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radeon_enc_code_fixed_bits(enc, 0x0, 1); /* chroma loc info present flag */
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/* chroma loc info present flag */
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radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.chroma_loc_info_present_flag, 1);
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if (pic->vui_info.flags.chroma_loc_info_present_flag) {
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radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_top_field);
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radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_bottom_field);
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}
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radeon_enc_code_fixed_bits(enc, 0x0, 1); /* neutral chroma indication flag */
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radeon_enc_code_fixed_bits(enc, 0x0, 1); /* field seq flag */
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radeon_enc_code_fixed_bits(enc, 0x0, 1); /* frame field info present flag */
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