radeonsi/vcn: Set H264/HEVC chroma sample location in bitstream

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25078>
This commit is contained in:
David Rosca 2023-09-06 12:17:53 +02:00 committed by Marge Bot
parent 8e76b8fb35
commit d57241d290
4 changed files with 33 additions and 3 deletions

View file

@ -546,6 +546,7 @@ typedef struct rvcn_enc_vui_info_s
uint32_t timing_info_present_flag : 1;
uint32_t video_signal_type_present_flag : 1;
uint32_t colour_description_present_flag : 1;
uint32_t chroma_loc_info_present_flag : 1;
} flags;
uint32_t aspect_ratio_idc;
uint32_t sar_width;
@ -557,6 +558,8 @@ typedef struct rvcn_enc_vui_info_s
uint32_t colour_primaries;
uint32_t transfer_characteristics;
uint32_t matrix_coefficients;
uint32_t chroma_sample_loc_type_top_field;
uint32_t chroma_sample_loc_type_bottom_field;
}rvcn_enc_vui_info;
typedef struct rvcn_enc_input_format_s

View file

@ -173,6 +173,8 @@ static void radeon_vcn_enc_h264_get_vui_param(struct radeon_encoder *enc,
pic->seq.vui_flags.video_signal_type_present_flag;
enc->enc_pic.vui_info.flags.colour_description_present_flag =
pic->seq.vui_flags.colour_description_present_flag;
enc->enc_pic.vui_info.flags.chroma_loc_info_present_flag =
pic->seq.vui_flags.chroma_loc_info_present_flag;
enc->enc_pic.vui_info.aspect_ratio_idc = pic->seq.aspect_ratio_idc;
enc->enc_pic.vui_info.sar_width = pic->seq.sar_width;
enc->enc_pic.vui_info.sar_height = pic->seq.sar_height;
@ -183,6 +185,10 @@ static void radeon_vcn_enc_h264_get_vui_param(struct radeon_encoder *enc,
enc->enc_pic.vui_info.colour_primaries = pic->seq.colour_primaries;
enc->enc_pic.vui_info.transfer_characteristics = pic->seq.transfer_characteristics;
enc->enc_pic.vui_info.matrix_coefficients = pic->seq.matrix_coefficients;
enc->enc_pic.vui_info.chroma_sample_loc_type_top_field =
pic->seq.chroma_sample_loc_type_top_field;
enc->enc_pic.vui_info.chroma_sample_loc_type_bottom_field =
pic->seq.chroma_sample_loc_type_bottom_field;
}
/* only checking the first slice to get num of mbs in slice to
@ -401,6 +407,8 @@ static void radeon_vcn_enc_hevc_get_vui_param(struct radeon_encoder *enc,
pic->seq.vui_flags.video_signal_type_present_flag;
enc->enc_pic.vui_info.flags.colour_description_present_flag =
pic->seq.vui_flags.colour_description_present_flag;
enc->enc_pic.vui_info.flags.chroma_loc_info_present_flag =
pic->seq.vui_flags.chroma_loc_info_present_flag;
enc->enc_pic.vui_info.aspect_ratio_idc = pic->seq.aspect_ratio_idc;
enc->enc_pic.vui_info.sar_width = pic->seq.sar_width;
enc->enc_pic.vui_info.sar_height = pic->seq.sar_height;
@ -411,6 +419,10 @@ static void radeon_vcn_enc_hevc_get_vui_param(struct radeon_encoder *enc,
enc->enc_pic.vui_info.colour_primaries = pic->seq.colour_primaries;
enc->enc_pic.vui_info.transfer_characteristics = pic->seq.transfer_characteristics;
enc->enc_pic.vui_info.matrix_coefficients = pic->seq.matrix_coefficients;
enc->enc_pic.vui_info.chroma_sample_loc_type_top_field =
pic->seq.chroma_sample_loc_type_top_field;
enc->enc_pic.vui_info.chroma_sample_loc_type_bottom_field =
pic->seq.chroma_sample_loc_type_bottom_field;
}
/* only checking the first slice to get num of ctbs in slice to

View file

@ -316,7 +316,12 @@ static void radeon_enc_nalu_sps(struct radeon_encoder *enc)
radeon_enc_code_fixed_bits(enc, pic->vui_info.matrix_coefficients, 8);
}
}
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* chroma loc info present flag */
/* chroma loc info present flag */
radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.chroma_loc_info_present_flag, 1);
if (pic->vui_info.flags.chroma_loc_info_present_flag) {
radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_top_field);
radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_bottom_field);
}
/* timing info present flag */
radeon_enc_code_fixed_bits(enc, (pic->vui_info.flags.timing_info_present_flag), 1);
if (pic->vui_info.flags.timing_info_present_flag) {
@ -456,7 +461,12 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
radeon_enc_code_fixed_bits(enc, pic->vui_info.matrix_coefficients, 8);
}
}
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* chroma loc info present flag */
/* chroma loc info present flag */
radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.chroma_loc_info_present_flag, 1);
if (pic->vui_info.flags.chroma_loc_info_present_flag) {
radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_top_field);
radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_bottom_field);
}
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* neutral chroma indication flag */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* field seq flag */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* frame field info present flag */

View file

@ -348,7 +348,12 @@ static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
radeon_enc_code_fixed_bits(enc, pic->vui_info.matrix_coefficients, 8);
}
}
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* chroma loc info present flag */
/* chroma loc info present flag */
radeon_enc_code_fixed_bits(enc, pic->vui_info.flags.chroma_loc_info_present_flag, 1);
if (pic->vui_info.flags.chroma_loc_info_present_flag) {
radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_top_field);
radeon_enc_code_ue(enc, pic->vui_info.chroma_sample_loc_type_bottom_field);
}
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* neutral chroma indication flag */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* field seq flag */
radeon_enc_code_fixed_bits(enc, 0x0, 1); /* frame field info present flag */