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ir3: remove unnecessary tessellation epilogue

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The tessellation epilogue was emitted as an empty predt/prede pair which
has no functional use so can be removed.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27982>
This commit is contained in:
Job Noorman 2024-03-05 15:00:17 +01:00 • committed by Marge Bot
parent 44b080af07
commit d56f1abd72
3 changed files with 0 additions and 58 deletions
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8
src/compiler/nir/nir_intrinsics.py
View file

@ -1312,14 +1312,6 @@ system_value("subgroup_id_shift_ir3", 1)
intrinsic("load_frag_coord_unscaled_ir3", dest_comp=4,
flags=[CAN_ELIMINATE, CAN_REORDER], bit_sizes=[32])
# IR3-specific intrinsics for tessellation control shaders. cond_end_ir3 end
# the shader when src0 is false and is used to narrow down the TCS shader to
# just thread 0 before writing out tessellation levels.
intrinsic("cond_end_ir3", src_comp=[1])
# end_patch_ir3 is used just before thread 0 exist the TCS and presumably
# signals the TE that the patch is complete and can be tessellated.
intrinsic("end_patch_ir3")
# Per-view gl_FragSizeEXT and gl_FragCoord offset.
intrinsic("load_frag_size_ir3", src_comp=[1], dest_comp=2, indices=[RANGE],
flags=[CAN_ELIMINATE, CAN_REORDER], bit_sizes=[32])

33
src/freedreno/ir3/ir3_compiler_nir.c
View file

@ -2276,15 +2276,6 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
break;
case nir_intrinsic_end_patch_ir3:
assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
struct ir3_instruction *end = ir3_PREDE(b);
array_insert(b, b->keeps, end);
end->barrier_class = IR3_BARRIER_EVERYTHING;
end->barrier_conflict = IR3_BARRIER_EVERYTHING;
break;
case nir_intrinsic_store_global_ir3:
ctx->funcs->emit_intrinsic_store_global_ir3(ctx, intr);
break;
@ -2628,30 +2619,6 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
break;
}
case nir_intrinsic_cond_end_ir3: {
struct ir3_instruction *cond, *kill;
src = ir3_get_src(ctx, &intr->src[0]);
cond = src[0];
/* NOTE: only cmps.*.* can write p0.x: */
struct ir3_instruction *zero =
create_immed_typed(b, 0, is_half(cond) ? TYPE_U16 : TYPE_U32);
cond = ir3_CMPS_S(b, cond, 0, zero, 0);
cond->cat2.condition = IR3_COND_NE;
/* condition always goes in predicate register: */
cond->dsts[0]->flags |= IR3_REG_PREDICATE;
kill = ir3_PREDT(b, cond, IR3_REG_PREDICATE);
kill->barrier_class = IR3_BARRIER_EVERYTHING;
kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
array_insert(b, b->keeps, kill);
break;
}
case nir_intrinsic_vote_any:
case nir_intrinsic_vote_all: {
struct ir3_instruction *src = ir3_get_src(ctx, &intr->src[0])[0];

17
src/freedreno/ir3/ir3_nir_lower_tess.c
View file

@ -648,17 +648,6 @@ lower_tess_ctrl_block(nir_block *block, nir_builder *b, struct state *state)
}
}
static void
emit_tess_epilouge(nir_builder *b, struct state *state)
{
/* Insert endpatch instruction:
*
* TODO we should re-work this to use normal flow control.
*/
nir_end_patch_ir3(b);
}
void
ir3_nir_lower_tess_ctrl(nir_shader *shader, struct ir3_shader_variant *v,
unsigned topology)
@ -724,12 +713,6 @@ ir3_nir_lower_tess_ctrl(nir_shader *shader, struct ir3_shader_variant *v,
b.cursor = nir_after_cf_list(&nif->then_list);
/* Insert conditional exit for threads invocation id != 0 */
nir_def *iid0_cond = nir_ieq_imm(&b, iid, 0);
nir_cond_end_ir3(&b, iid0_cond);
emit_tess_epilouge(&b, &state);
nir_pop_if(&b, nif);
nir_metadata_preserve(impl, nir_metadata_none);