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radeonsi: set PA_SC_EDGERULE according to bottom_edge_rule state

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Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15965>
This commit is contained in:
Marek Olšák 2022-03-22 02:12:45 -04:00 • committed by Marge Bot
parent 91bc463a51
commit d54236ec41
2 changed files with 24 additions and 7 deletions
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4
src/gallium/drivers/radeonsi/ci/traces-radeonsi.yml
View file

@ -17,11 +17,11 @@ traces:
- path: 0ad/0ad.trace
expectations:
- device: gl-radeonsi-stoney
checksum: 1a089d8584a9e68e7ab08eada954741b
checksum: 8d71757cb74f8d71bf87c8af7e7f725a
- path: pathfinder/demo.trace
expectations:
- device: gl-radeonsi-stoney
checksum: c81c85f9b247dd1b06c3dd5b669cc283
checksum: 86318ec31a55a1246cb4a136a15475fd
- path: pathfinder/canvas_moire.trace
expectations:
- device: gl-radeonsi-stoney

27
src/gallium/drivers/radeonsi/si_state.c
View file

@ -1051,6 +1051,28 @@ static void *si_create_rs_state(struct pipe_context *ctx, const struct pipe_rast
polygon_mode_enabled ||
rs->perpendicular_end_caps : 0));
if (state->bottom_edge_rule) {
/* OpenGL windows should set this. */
si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
S_028230_ER_TRI(0xA) |
S_028230_ER_POINT(0x5) |
S_028230_ER_RECT(0x9) |
S_028230_ER_LINE_LR(0x29) |
S_028230_ER_LINE_RL(0x29) |
S_028230_ER_LINE_TB(0xA) |
S_028230_ER_LINE_BT(0xA));
} else {
/* OpenGL FBOs and Direct3D should set this. */
si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
S_028230_ER_TRI(0xA) |
S_028230_ER_POINT(0xA) |
S_028230_ER_RECT(0xA) |
S_028230_ER_LINE_LR(0x1A) |
S_028230_ER_LINE_RL(0x26) |
S_028230_ER_LINE_TB(0xA) |
S_028230_ER_LINE_BT(0xA));
}
if (!rs->uses_poly_offset)
return rs;
@ -5406,11 +5428,6 @@ void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing)
si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
if (!has_clear_state) {
si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
S_028230_ER_TRI(0xA) | S_028230_ER_POINT(0xA) | S_028230_ER_RECT(0xA) |
/* Required by DX10_DIAMOND_TEST_ENA: */
S_028230_ER_LINE_LR(0x1A) | S_028230_ER_LINE_RL(0x26) |
S_028230_ER_LINE_TB(0xA) | S_028230_ER_LINE_BT(0xA));
si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);