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gallium/radeon: enable suballocations for VRAM with no CPU access

Browse source 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-06-29 18:33:05 +02:00
parent 64e5577cac
commit d4fac1e1d7
4 changed files with 21 additions and 4 deletions
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4
src/gallium/drivers/radeon/r600_buffer_common.c
View file

@ -176,8 +176,10 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen,
*/ */
if (!rscreen->info.has_dedicated_vram && if (!rscreen->info.has_dedicated_vram &&
(rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) && (rscreen->info.drm_major < 3 || rscreen->info.drm_minor < 6) &&
res->domains == RADEON_DOMAIN_VRAM) res->domains == RADEON_DOMAIN_VRAM) {
res->domains = RADEON_DOMAIN_VRAM_GTT; res->domains = RADEON_DOMAIN_VRAM_GTT;
res->flags &= ~RADEON_FLAG_NO_CPU_ACCESS; /* disallowed with VRAM_GTT */
}
if (rscreen->debug_flags & DBG_NO_WC) if (rscreen->debug_flags & DBG_NO_WC)
res->flags &= ~RADEON_FLAG_GTT_WC; res->flags &= ~RADEON_FLAG_GTT_WC;

13
src/gallium/drivers/radeon/radeon_winsys.h
View file

@ -659,6 +659,7 @@ static inline void radeon_emit_array(struct radeon_winsys_cs *cs,
} }
enum radeon_heap { enum radeon_heap {
RADEON_HEAP_VRAM_NO_CPU_ACCESS,
RADEON_HEAP_VRAM, RADEON_HEAP_VRAM,
RADEON_HEAP_VRAM_GTT, /* combined heaps */ RADEON_HEAP_VRAM_GTT, /* combined heaps */
RADEON_HEAP_GTT_WC, RADEON_HEAP_GTT_WC,
@ -669,6 +670,7 @@ enum radeon_heap {
static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap) static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap heap)
{ {
switch (heap) { switch (heap) {
case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
case RADEON_HEAP_VRAM: case RADEON_HEAP_VRAM:
return RADEON_DOMAIN_VRAM; return RADEON_DOMAIN_VRAM;
case RADEON_HEAP_VRAM_GTT: case RADEON_HEAP_VRAM_GTT:
@ -685,6 +687,8 @@ static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap hea
static inline unsigned radeon_flags_from_heap(enum radeon_heap heap) static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
{ {
switch (heap) { switch (heap) {
case RADEON_HEAP_VRAM_NO_CPU_ACCESS:
return RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS;
case RADEON_HEAP_VRAM: case RADEON_HEAP_VRAM:
case RADEON_HEAP_VRAM_GTT: case RADEON_HEAP_VRAM_GTT:
case RADEON_HEAP_GTT_WC: case RADEON_HEAP_GTT_WC:
@ -701,13 +705,18 @@ static inline int radeon_get_heap_index(enum radeon_bo_domain domain,
{ {
/* VRAM implies WC (write combining) */ /* VRAM implies WC (write combining) */
assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC); assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
/* NO_CPU_ACCESS implies VRAM only. */
assert(!(flags & RADEON_FLAG_NO_CPU_ACCESS) || domain == RADEON_DOMAIN_VRAM);
/* Unsupported flags: NO_CPU_ACCESS, NO_SUBALLOC, SPARSE. */ /* Unsupported flags: NO_SUBALLOC, SPARSE. */
if (flags & ~RADEON_FLAG_GTT_WC) if (flags & ~(RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS))
return -1; return -1;
switch (domain) { switch (domain) {
case RADEON_DOMAIN_VRAM: case RADEON_DOMAIN_VRAM:
if (flags & RADEON_FLAG_NO_CPU_ACCESS)
return RADEON_HEAP_VRAM_NO_CPU_ACCESS;
else
return RADEON_HEAP_VRAM; return RADEON_HEAP_VRAM;
case RADEON_DOMAIN_VRAM_GTT: case RADEON_DOMAIN_VRAM_GTT:
return RADEON_HEAP_VRAM_GTT; return RADEON_HEAP_VRAM_GTT;

3
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
View file

@ -1138,6 +1138,9 @@ amdgpu_bo_create(struct radeon_winsys *rws,
/* VRAM implies WC. This is not optional. */ /* VRAM implies WC. This is not optional. */
assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC); assert(!(domain & RADEON_DOMAIN_VRAM) || flags & RADEON_FLAG_GTT_WC);
/* NO_CPU_ACCESS is valid with VRAM only. */
assert(domain == RADEON_DOMAIN_VRAM || !(flags & RADEON_FLAG_NO_CPU_ACCESS));
/* Sub-allocate small buffers from slabs. */ /* Sub-allocate small buffers from slabs. */
if (!(flags & (RADEON_FLAG_NO_SUBALLOC | RADEON_FLAG_SPARSE)) && if (!(flags & (RADEON_FLAG_NO_SUBALLOC | RADEON_FLAG_SPARSE)) &&
size <= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2) && size <= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2) &&

3
src/gallium/winsys/radeon/drm/radeon_drm_bo.c
View file

@ -925,6 +925,9 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
/* VRAM implies WC. This is not optional. */ /* VRAM implies WC. This is not optional. */
if (domain & RADEON_DOMAIN_VRAM) if (domain & RADEON_DOMAIN_VRAM)
flags |= RADEON_FLAG_GTT_WC; flags |= RADEON_FLAG_GTT_WC;
/* NO_CPU_ACCESS is valid with VRAM only. */
if (domain != RADEON_DOMAIN_VRAM)
flags &= ~RADEON_FLAG_NO_CPU_ACCESS;
/* Sub-allocate small buffers from slabs. */ /* Sub-allocate small buffers from slabs. */
if (!(flags & RADEON_FLAG_NO_SUBALLOC) && if (!(flags & RADEON_FLAG_NO_SUBALLOC) &&