From d4cd33630a9b90b95390f10d3aaa52f6f5e20245 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Mon, 5 Dec 2022 20:27:59 +0200 Subject: [PATCH] intel: add missing restriction on fragment simd dispatch Signed-off-by: Lionel Landwerlin Cc: mesa-stable Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7755 Reviewed-by: Ivan Briano Tested-by: Mark Janes Part-of: --- src/intel/compiler/brw_compiler.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 06d0c4d26ea..938845895ee 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -999,6 +999,14 @@ brw_fs_get_dispatch_enables(const struct intel_device_info *devinfo, *enable_32 = prog_data->dispatch_32; if (prog_data->persample_dispatch) { + /* TGL PRMs, Volume 2d: Command Reference: Structures: + * 3DSTATE_PS_BODY::32 Pixel Dispatch Enable: + * + * "Must not be enabled when dispatch rate is sample AND NUM_MULTISAMPLES > 1." + */ + if (devinfo->ver >= 12 && rasterization_samples > 1) + *enable_32 = false; + /* Starting with SandyBridge (where we first get MSAA), the different * pixel dispatch combinations are grouped into classifications A * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On most hardware