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i965: Introduce a new brw_inst API.
This is similar to gen8_instruction, and will eventually replace it. For now nothing uses this, but we can incrementally convert. The new API takes the existing brw_instruction pointers to ease conversion; when done, we can simply drop the old structure and rename struct brw_instruction -> brw_inst. v2: (by Matt Turner) Make JIP/UIP functions take a signed argument. v3: (by Kenneth Graunke) - Make Gen4-6 jump target functions take a signed argument. - Fix indirect align1 AddrImm bits on Gen4-7. - Fix SFID on Sandybridge to use bits 27:24. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> [v1, v3+] Signed-off-by: Matt Turner <mattst88@gmail.com> [v2] Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Kenneth Graunke
parent
05040d6f8f
commit
d49a9ca8c2
1 changed files with 707 additions and 0 deletions
707
src/mesa/drivers/dri/i965/brw_inst.h
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src/mesa/drivers/dri/i965/brw_inst.h
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@ -0,0 +1,707 @@
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/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/**
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* @file brw_inst.h
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*
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* A representation of i965 EU assembly instructions, with helper methods to
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* get and set various fields. This is the actual hardware format.
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*/
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#ifndef BRW_INST_H
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#define BRW_INST_H
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#include <stdint.h>
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#include "brw_context.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct brw_instruction;
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typedef struct {
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uint64_t data[2];
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} brw_inst;
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static inline uint64_t brw_inst_bits(struct brw_instruction *inst,
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unsigned high, unsigned low);
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static inline void brw_inst_set_bits(struct brw_instruction *inst,
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unsigned high, unsigned low,
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uint64_t value);
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#define FC(name, high, low, assertions) \
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static inline void \
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brw_inst_set_##name(const struct brw_context *brw, \
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struct brw_instruction *inst, uint64_t v) \
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{ \
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assert(assertions); \
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brw_inst_set_bits(inst, high, low, v); \
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} \
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static inline uint64_t \
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brw_inst_##name(const struct brw_context *brw, \
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struct brw_instruction *inst) \
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{ \
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assert(assertions); \
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return brw_inst_bits(inst, high, low); \
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}
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/* A simple macro for fields which stay in the same place on all generations. */
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#define F(name, high, low) FC(name, high, low, true)
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#define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
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unsigned high, low; \
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if (brw->gen >= 8) { \
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high = hi8; low = lo8; \
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} else if (brw->gen >= 7) { \
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high = hi7; low = lo7; \
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} else if (brw->gen >= 6) { \
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high = hi6; low = lo6; \
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} else if (brw->gen >= 5) { \
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high = hi5; low = lo5; \
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} else if (brw->is_g4x) { \
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high = hi45; low = lo45; \
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} else { \
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high = hi4; low = lo4; \
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} \
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assert(((int) high) != -1 && ((int) low) != -1); \
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/* A general macro for cases where the field has moved to several different
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* bit locations across generations. GCC appears to combine cases where the
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* bits are identical, removing some of the inefficiency.
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*/
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#define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
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static inline void \
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brw_inst_set_##name(const struct brw_context *brw, \
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struct brw_instruction *inst, uint64_t value) \
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{ \
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BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
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brw_inst_set_bits(inst, high, low, value); \
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} \
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static inline uint64_t \
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brw_inst_##name(const struct brw_context *brw, struct brw_instruction *inst) \
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{ \
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BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
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return brw_inst_bits(inst, high, low); \
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}
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/* A macro for fields which moved as of Gen8+. */
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#define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
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FF(name, \
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/* 4: */ gen4_high, gen4_low, \
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/* 4.5: */ gen4_high, gen4_low, \
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/* 5: */ gen4_high, gen4_low, \
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/* 6: */ gen4_high, gen4_low, \
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/* 7: */ gen4_high, gen4_low, \
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/* 8: */ gen8_high, gen8_low);
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F(src1_vstride, 120, 117)
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F(src1_width, 116, 114)
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F(src1_da16_swiz_w, 115, 114)
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F(src1_da16_swiz_z, 113, 112)
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F(src1_hstride, 113, 112)
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F(src1_address_mode, 111, 111)
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/** Src1.SrcMod @{ */
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F(src1_negate, 110, 110)
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F(src1_abs, 109, 109)
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/** @} */
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F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
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F(src1_da_reg_nr, 108, 101)
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F(src1_da16_subreg_nr, 100, 100)
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F(src1_da1_subreg_nr, 100, 96)
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F(src1_da16_swiz_y, 99, 98)
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F(src1_da16_swiz_x, 97, 96)
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F8(src1_reg_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
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F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
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F(src0_vstride, 88, 85)
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F(src0_width, 84, 82)
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F(src0_da16_swiz_w, 83, 82)
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F(src0_da16_swiz_z, 81, 80)
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F(src0_hstride, 81, 80)
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F(src0_address_mode, 79, 79)
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/** Src0.SrcMod @{ */
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F(src0_negate, 78, 78)
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F(src0_abs, 77, 77)
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/** @} */
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F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
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F(src0_da_reg_nr, 76, 69)
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F(src0_da16_subreg_nr, 68, 68)
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F(src0_da1_subreg_nr, 68, 64)
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F(src0_da16_swiz_y, 67, 66)
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F(src0_da16_swiz_x, 65, 64)
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F(dst_address_mode, 63, 63)
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F(dst_hstride, 62, 61)
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F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
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F(dst_da_reg_nr, 60, 53)
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F(dst_da16_subreg_nr, 52, 52)
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F(dst_da1_subreg_nr, 52, 48)
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F(da16_writemask, 51, 48) /* Dst.ChanEn */
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F8(src0_reg_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
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F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
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F8(dst_reg_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
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F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
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F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
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FF(flag_reg_nr,
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/* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
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/* 7: */ 90, 90,
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/* 8: */ 33, 33)
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F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
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F(saturate, 31, 31)
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FC(branch_control, 30, 30, brw->gen >= 8)
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F(debug_control, 30, 30)
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F(cmpt_control, 29, 29)
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F(acc_wr_control, 28, 28)
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F(cond_modifier, 27, 24)
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FC(math_function, 27, 24, brw->gen >= 6)
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F(exec_size, 23, 21)
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F(pred_inv, 20, 20)
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F(pred_control, 19, 16)
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F(thread_control, 15, 14)
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F(qtr_control, 13, 12)
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FF(nib_control,
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/* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
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/* 7: */ 47, 47,
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/* 8: */ 11, 11)
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F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
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F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
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F(access_mode, 8, 8)
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/* Bit 7 is Reserved (for future Opcode expansion) */
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F(opcode, 6, 0)
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/**
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* Three-source instructions:
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* @{
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*/
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F(3src_src2_reg_nr, 125, 118)
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F(3src_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */
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F(3src_src2_swizzle, 114, 107)
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F(3src_src2_rep_ctrl, 106, 106)
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F(3src_src1_reg_nr, 104, 97)
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F(3src_src1_subreg_nr, 96, 94) /* Extra discontiguous bit on CHV? */
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F(3src_src1_swizzle, 93, 86)
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F(3src_src1_rep_ctrl, 85, 85)
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F(3src_src0_reg_nr, 83, 76)
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F(3src_src0_subreg_nr, 75, 73) /* Extra discontiguous bit on CHV? */
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F(3src_src0_swizzle, 72, 65)
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F(3src_src0_rep_ctrl, 64, 64)
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F(3src_dst_reg_nr, 63, 56)
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F(3src_dst_subreg_nr, 55, 53)
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F(3src_dst_writemask, 52, 49)
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F8(3src_nib_ctrl, 47, 47, 11, 11) /* only exists on IVB+ */
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F8(3src_dst_type, 45, 44, 48, 46) /* only exists on IVB+ */
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F8(3src_src_type, 43, 42, 45, 43)
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F8(3src_src2_negate, 41, 41, 42, 42)
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F8(3src_src2_abs, 40, 40, 41, 41)
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F8(3src_src1_negate, 39, 39, 40, 40)
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F8(3src_src1_abs, 38, 38, 39, 39)
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F8(3src_src0_negate, 37, 37, 38, 38)
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F8(3src_src0_abs, 36, 36, 37, 37)
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F8(3src_flag_reg_nr, 34, 34, 33, 33)
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F8(3src_flag_subreg_nr, 33, 33, 32, 32)
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FF(3src_dst_reg_file,
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/* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
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/* 6: */ 32, 32,
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/* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
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F(3src_saturate, 31, 31)
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F(3src_debug_control, 30, 30)
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F(3src_cmpt_control, 29, 29)
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F(3src_acc_wr_control, 28, 28)
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F(3src_cond_modifier, 27, 24)
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F(3src_exec_size, 23, 21)
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F(3src_pred_inv, 20, 20)
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F(3src_pred_control, 19, 16)
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F(3src_thread_control, 15, 14)
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F(3src_qtr_control, 13, 12)
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F8(3src_no_dd_check, 11, 11, 10, 10)
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F8(3src_no_dd_clear, 10, 10, 9, 9)
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F8(3src_mask_control, 9, 9, 34, 34)
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F(3src_access_mode, 8, 8)
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/* Bit 7 is Reserved (for future Opcode expansion) */
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F(3src_opcode, 6, 0)
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/** @} */
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/**
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* Flow control instruction bits:
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* @{
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*/
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static inline void
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brw_inst_set_uip(const struct brw_context *brw,
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struct brw_instruction *inst, int32_t value)
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{
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assert(brw->gen >= 6);
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if (brw->gen >= 8) {
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brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
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} else {
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assert(value <= (1 << 16) - 1);
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assert(value > -(1 << 16));
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brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
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}
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}
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static inline int32_t
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brw_inst_uip(const struct brw_context *brw, struct brw_instruction *inst)
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{
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assert(brw->gen >= 6);
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if (brw->gen >= 8) {
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return brw_inst_bits(inst, 95, 64);
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} else {
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return (int16_t)brw_inst_bits(inst, 127, 112);
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}
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}
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static inline void
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brw_inst_set_jip(const struct brw_context *brw,
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struct brw_instruction *inst, int32_t value)
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{
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assert(brw->gen >= 6);
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if (brw->gen >= 8) {
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brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
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} else {
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assert(value <= (1 << 16) - 1);
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assert(value > -(1 << 16));
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brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
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}
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}
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static inline int32_t
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brw_inst_jip(const struct brw_context *brw, struct brw_instruction *inst)
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{
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assert(brw->gen >= 6);
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if (brw->gen >= 8) {
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return brw_inst_bits(inst, 127, 96);
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} else {
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return (int16_t)brw_inst_bits(inst, 111, 96);
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}
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}
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/** Like FC, but using int16_t to handle negative jump targets. */
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#define FJ(name, high, low, assertions) \
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static inline void \
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brw_inst_set_##name(const struct brw_context *brw, brw_inst *inst, int16_t v) \
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{ \
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assert(assertions); \
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assert(v <= (1 << 16) - 1); \
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assert(v > -(1 << 16)); \
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brw_inst_set_bits(inst, high, low, (uint16_t) v); \
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} \
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static inline int16_t \
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brw_inst_##name(const struct brw_context *brw, brw_inst *inst) \
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{ \
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assert(assertions); \
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return brw_inst_bits(inst, high, low); \
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}
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FJ(gen6_jump_count, 63, 48, brw->gen == 6)
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FJ(gen4_jump_count, 111, 96, brw->gen < 6)
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FC(gen4_pop_count, 115, 112, brw->gen < 6)
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/** @} */
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/**
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* Fields for SEND messages:
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* @{
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*/
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F(eot, 127, 127)
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FF(mlen,
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/* 4: */ 119, 116,
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/* 4.5: */ 119, 116,
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/* 5: */ 124, 121,
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/* 6: */ 124, 121,
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/* 7: */ 124, 121,
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/* 8: */ 124, 121);
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FF(rlen,
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/* 4: */ 115, 112,
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/* 4.5: */ 115, 112,
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/* 5: */ 120, 116,
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/* 6: */ 120, 116,
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/* 7: */ 120, 116,
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/* 8: */ 120, 116);
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FF(header_present,
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/* 4: doesn't exist */ -1, -1, -1, -1,
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/* 5: */ 115, 115,
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/* 6: */ 115, 115,
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/* 7: */ 115, 115,
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/* 8: */ 115, 115)
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FF(function_control,
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/* 4: */ 111, 96,
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/* 4.5: */ 111, 96,
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/* 5: */ 114, 96,
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/* 6: */ 114, 96,
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/* 7: */ 114, 96,
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/* 8: */ 114, 96)
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FF(sfid,
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/* 4: */ 123, 120, /* called msg_target */
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/* 4.5 */ 123, 120,
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/* 5: */ 95, 92,
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/* 6: */ 27, 24,
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/* 7: */ 27, 24,
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/* 8: */ 27, 24)
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FC(base_mrf, 27, 24, brw->gen < 6);
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/** @} */
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/* Message descriptor bits */
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#define MD(x) (x + 96)
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/**
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* URB message function control bits:
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* @{
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*/
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FF(urb_per_slot_offset,
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/* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
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/* 7: */ MD(16), MD(16),
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/* 8: */ MD(17), MD(17))
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FC(urb_complete, MD(15), MD(15), brw->gen < 8)
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FC(urb_used, MD(14), MD(14), brw->gen < 7)
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FC(urb_allocate, MD(13), MD(13), brw->gen < 7)
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FF(urb_swizzle_control,
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/* 4: */ MD(11), MD(10),
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/* 4.5: */ MD(11), MD(10),
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/* 5: */ MD(11), MD(10),
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||||
/* 6: */ MD(11), MD(10),
|
||||
/* 7: */ MD(14), MD(14),
|
||||
/* 8: */ MD(15), MD(15))
|
||||
FF(urb_global_offset,
|
||||
/* 4: */ MD( 9), MD(4),
|
||||
/* 4.5: */ MD( 9), MD(4),
|
||||
/* 5: */ MD( 9), MD(4),
|
||||
/* 6: */ MD( 9), MD(4),
|
||||
/* 7: */ MD(13), MD(3),
|
||||
/* 8: */ MD(14), MD(4))
|
||||
FF(urb_opcode,
|
||||
/* 4: */ MD( 3), MD(0),
|
||||
/* 4.5: */ MD( 3), MD(0),
|
||||
/* 5: */ MD( 3), MD(0),
|
||||
/* 6: */ MD( 3), MD(0),
|
||||
/* 7: */ MD( 2), MD(0),
|
||||
/* 8: */ MD( 3), MD(0))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* Gen4-5 math messages:
|
||||
* @{
|
||||
*/
|
||||
FC(math_msg_data_type, MD(7), MD(7), brw->gen < 6)
|
||||
FC(math_msg_saturate, MD(6), MD(6), brw->gen < 6)
|
||||
FC(math_msg_precision, MD(5), MD(5), brw->gen < 6)
|
||||
FC(math_msg_signed_int, MD(4), MD(4), brw->gen < 6)
|
||||
FC(math_msg_function, MD(3), MD(0), brw->gen < 6)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* Sampler message function control bits:
|
||||
* @{
|
||||
*/
|
||||
FF(sampler_simd_mode,
|
||||
/* 4: doesn't exist */ -1, -1, -1, -1,
|
||||
/* 5: */ MD(17), MD(16),
|
||||
/* 6: */ MD(17), MD(16),
|
||||
/* 7: */ MD(18), MD(17),
|
||||
/* 8: */ MD(18), MD(17))
|
||||
FF(sampler_msg_type,
|
||||
/* 4: */ MD(15), MD(14),
|
||||
/* 4.5: */ MD(15), MD(12),
|
||||
/* 5: */ MD(15), MD(12),
|
||||
/* 6: */ MD(15), MD(12),
|
||||
/* 7: */ MD(16), MD(12),
|
||||
/* 8: */ MD(16), MD(12))
|
||||
FC(sampler_return_format, MD(13), MD(12), brw->gen == 4 && !brw->is_g4x)
|
||||
F(sampler, MD(11), MD(8))
|
||||
F(binding_table_index, MD( 7), MD(0)) /* also used by other messages */
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* Data port message function control bits:
|
||||
* @{
|
||||
*/
|
||||
FC(dp_category, MD(18), MD(18), brw->gen >= 7)
|
||||
|
||||
/* Gen4-5 store fields in different bits for read/write messages. */
|
||||
FF(dp_read_msg_type,
|
||||
/* 4: */ MD(13), MD(12),
|
||||
/* 4.5: */ MD(13), MD(11),
|
||||
/* 5: */ MD(13), MD(11),
|
||||
/* 6: */ MD(16), MD(13),
|
||||
/* 7: */ MD(17), MD(14),
|
||||
/* 8: */ MD(17), MD(14))
|
||||
FF(dp_write_msg_type,
|
||||
/* 4: */ MD(14), MD(12),
|
||||
/* 4.5: */ MD(14), MD(12),
|
||||
/* 5: */ MD(14), MD(12),
|
||||
/* 6: */ MD(16), MD(13),
|
||||
/* 7: */ MD(17), MD(14),
|
||||
/* 8: */ MD(17), MD(14))
|
||||
FF(dp_read_msg_control,
|
||||
/* 4: */ MD(11), MD( 8),
|
||||
/* 4.5: */ MD(10), MD( 8),
|
||||
/* 5: */ MD(10), MD( 8),
|
||||
/* 6: */ MD(12), MD( 8),
|
||||
/* 7: */ MD(13), MD( 8),
|
||||
/* 8: */ MD(13), MD( 8))
|
||||
FF(dp_write_msg_control,
|
||||
/* 4: */ MD(11), MD( 8),
|
||||
/* 4.5: */ MD(11), MD( 8),
|
||||
/* 5: */ MD(11), MD( 8),
|
||||
/* 6: */ MD(12), MD( 8),
|
||||
/* 7: */ MD(13), MD( 8),
|
||||
/* 8: */ MD(13), MD( 8))
|
||||
FC(dp_read_target_cache, MD(15), MD(14), brw->gen < 6);
|
||||
|
||||
FF(dp_write_commit,
|
||||
/* 4: */ MD(15), MD(15),
|
||||
/* 4.5: */ MD(15), MD(15),
|
||||
/* 5: */ MD(15), MD(15),
|
||||
/* 6: */ MD(17), MD(17),
|
||||
/* 7+: does not exist */ -1, -1, -1, -1)
|
||||
|
||||
/* Gen6+ use the same bit locations for everything. */
|
||||
FF(dp_msg_type,
|
||||
/* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
|
||||
-1, -1, -1, -1, -1, -1,
|
||||
/* 6: */ MD(16), MD(13),
|
||||
/* 7: */ MD(17), MD(14),
|
||||
/* 8: */ MD(17), MD(14))
|
||||
FF(dp_msg_control,
|
||||
/* 4: */ MD(11), MD( 8),
|
||||
/* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
|
||||
/* 6: */ MD(12), MD( 8),
|
||||
/* 7: */ MD(13), MD( 8),
|
||||
/* 8: */ MD(13), MD( 8))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* Scratch message bits (Gen7+):
|
||||
* @{
|
||||
*/
|
||||
FC(scratch_read_write, MD(17), MD(17), brw->gen >= 7) /* 0 = read, 1 = write */
|
||||
FC(scratch_type, MD(16), MD(16), brw->gen >= 7) /* 0 = OWord, 1 = DWord */
|
||||
FC(scratch_invalidate_after_read, MD(15), MD(15), brw->gen >= 7)
|
||||
FC(scratch_block_size, MD(13), MD(12), brw->gen >= 7)
|
||||
FC(scratch_addr_offset, MD(11), MD( 0), brw->gen >= 7)
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* Render Target message function control bits:
|
||||
* @{
|
||||
*/
|
||||
FF(rt_last,
|
||||
/* 4: */ MD(11), MD(11),
|
||||
/* 4.5: */ MD(11), MD(11),
|
||||
/* 5: */ MD(11), MD(11),
|
||||
/* 6: */ MD(12), MD(12),
|
||||
/* 7: */ MD(12), MD(12),
|
||||
/* 8: */ MD(12), MD(12))
|
||||
FC(rt_slot_group, MD(11), MD(11), brw->gen >= 6)
|
||||
F(rt_message_type, MD(10), MD( 8))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* Thread Spawn message function control bits:
|
||||
* @{
|
||||
*/
|
||||
F(ts_resource_select, MD( 4), MD( 4))
|
||||
F(ts_request_type, MD( 1), MD( 1))
|
||||
F(ts_opcode, MD( 0), MD( 0))
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
* Immediates:
|
||||
* @{
|
||||
*/
|
||||
static inline int
|
||||
brw_inst_imm_d(const struct brw_context *brw, struct brw_instruction *insn)
|
||||
{
|
||||
return brw_inst_bits(insn, 127, 96);
|
||||
}
|
||||
|
||||
static inline unsigned
|
||||
brw_inst_imm_ud(const struct brw_context *brw, struct brw_instruction *insn)
|
||||
{
|
||||
return brw_inst_bits(insn, 127, 96);
|
||||
}
|
||||
|
||||
static inline float
|
||||
brw_inst_imm_f(const struct brw_context *brw, struct brw_instruction *insn)
|
||||
{
|
||||
fi_type ft;
|
||||
ft.u = brw_inst_bits(insn, 127, 96);
|
||||
return ft.f;
|
||||
}
|
||||
|
||||
static inline void
|
||||
brw_inst_set_imm_d(const struct brw_context *brw,
|
||||
struct brw_instruction *insn, int value)
|
||||
{
|
||||
return brw_inst_set_bits(insn, 127, 96, value);
|
||||
}
|
||||
|
||||
static inline void
|
||||
brw_inst_set_imm_ud(const struct brw_context *brw,
|
||||
struct brw_instruction *insn, unsigned value)
|
||||
{
|
||||
return brw_inst_set_bits(insn, 127, 96, value);
|
||||
}
|
||||
|
||||
static inline void
|
||||
brw_inst_set_imm_f(const struct brw_context *brw,
|
||||
struct brw_instruction *insn, float value)
|
||||
{
|
||||
fi_type ft;
|
||||
ft.f = value;
|
||||
brw_inst_set_bits(insn, 127, 96, ft.u);
|
||||
}
|
||||
|
||||
/** @} */
|
||||
|
||||
/* The AddrImm fields are split into two discontiguous sections on Gen8+ */
|
||||
#define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
|
||||
static inline void \
|
||||
brw_inst_set_##reg##_ia1_addr_imm(const struct brw_context *brw, \
|
||||
struct brw_instruction *inst, \
|
||||
unsigned value) \
|
||||
{ \
|
||||
assert((value & ~0x3ff) == 0); \
|
||||
if (brw->gen >= 8) { \
|
||||
brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
|
||||
brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
|
||||
} else { \
|
||||
brw_inst_set_bits(inst, g4_high, g4_low, value); \
|
||||
} \
|
||||
} \
|
||||
static inline unsigned \
|
||||
brw_inst_##reg##_ia1_addr_imm(const struct brw_context *brw, \
|
||||
struct brw_instruction *inst) \
|
||||
{ \
|
||||
if (brw->gen >= 8) { \
|
||||
return brw_inst_bits(inst, g8_high, g8_low) | \
|
||||
(brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
|
||||
} else { \
|
||||
return brw_inst_bits(inst, g4_high, g4_low); \
|
||||
} \
|
||||
}
|
||||
|
||||
/* AddrImm[9:0] for Align1 Indirect Addressing */
|
||||
/* -Gen 4- ----Gen8---- */
|
||||
BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
|
||||
BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
|
||||
BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
|
||||
|
||||
#define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
|
||||
static inline void \
|
||||
brw_inst_set_##reg##_ia16_addr_imm(const struct brw_context *brw, \
|
||||
struct brw_instruction *inst, \
|
||||
unsigned value) \
|
||||
{ \
|
||||
assert((value & ~0x3ff) == 0); \
|
||||
if (brw->gen >= 8) { \
|
||||
brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
|
||||
brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
|
||||
} else { \
|
||||
brw_inst_set_bits(inst, g4_high, g4_low, value >> 9); \
|
||||
} \
|
||||
} \
|
||||
static inline unsigned \
|
||||
brw_inst_##reg##_ia16_addr_imm(const struct brw_context *brw, \
|
||||
struct brw_instruction *inst) \
|
||||
{ \
|
||||
if (brw->gen >= 8) { \
|
||||
return brw_inst_bits(inst, g8_high, g8_low) | \
|
||||
(brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
|
||||
} else { \
|
||||
return brw_inst_bits(inst, g4_high, g4_low); \
|
||||
} \
|
||||
}
|
||||
|
||||
/* AddrImm[9:0] for Align16 Indirect Addressing:
|
||||
* Compared to Align1, these are missing the low 4 bits.
|
||||
* -Gen 4- ----Gen8----
|
||||
*/
|
||||
BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
|
||||
BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
|
||||
BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
|
||||
|
||||
/**
|
||||
* Fetch a set of contiguous bits from the instruction.
|
||||
*
|
||||
* Bits indices range from 0..127; fields may not cross 64-bit boundaries.
|
||||
*/
|
||||
static inline uint64_t
|
||||
brw_inst_bits(struct brw_instruction *insn, unsigned high, unsigned low)
|
||||
{
|
||||
brw_inst *inst = (brw_inst *) insn;
|
||||
|
||||
/* We assume the field doesn't cross 64-bit boundaries. */
|
||||
const unsigned word = high / 64;
|
||||
assert(word == low / 64);
|
||||
|
||||
high %= 64;
|
||||
low %= 64;
|
||||
|
||||
const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
|
||||
|
||||
return (inst->data[word] & mask) >> low;
|
||||
}
|
||||
|
||||
/**
|
||||
* Set bits in the instruction, with proper shifting and masking.
|
||||
*
|
||||
* Bits indices range from 0..127; fields may not cross 64-bit boundaries.
|
||||
*/
|
||||
static inline void
|
||||
brw_inst_set_bits(struct brw_instruction *insn,
|
||||
unsigned high, unsigned low,
|
||||
uint64_t value)
|
||||
{
|
||||
brw_inst *inst = (brw_inst *) insn;
|
||||
|
||||
const unsigned word = high / 64;
|
||||
assert(word == low / 64);
|
||||
|
||||
high %= 64;
|
||||
low %= 64;
|
||||
|
||||
const uint64_t mask = (((1ull << (high - low + 1)) - 1) << low);
|
||||
|
||||
/* Make sure the supplied value actually fits in the given bitfield. */
|
||||
assert((value & (mask >> low)) == value);
|
||||
|
||||
inst->data[word] = (inst->data[word] & ~mask) | ((value << low) & mask);
|
||||
}
|
||||
|
||||
#undef BRW_IA16_ADDR_IMM
|
||||
#undef BRW_IA1_ADDR_IMM
|
||||
#undef MD
|
||||
#undef F8
|
||||
#undef FF
|
||||
#undef BOUNDS
|
||||
#undef F
|
||||
#undef FC
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Reference in a new issue