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anv: Defer flushing PIPE_CONTROL bits forbidden in CCS while in GPGPU mode

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Fixes: 313aeee8 ("anv: Use pending pipe control mechanism in flush_pipeline_select()
")

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7816
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20124>
(cherry picked from commit 77ecf9149c)
This commit is contained in:
Sviatoslav Peleshko 2022-11-30 07:05:51 +02:00 • committed by Eric Engestrom
parent b34f6c1559
commit d43425f7e0
3 changed files with 62 additions and 1 deletions
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2
.pick_status.json
View file

@ -4036,7 +4036,7 @@
"description": "anv: Defer flushing PIPE_CONTROL bits forbidden in CCS while in GPGPU mode",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "313aeee84bc0eeb93766c0349dcc0ff2d5ba6574"
},

18
src/intel/vulkan/anv_private.h
View file

@ -2127,6 +2127,24 @@ enum anv_pipe_bits {
ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \
ANV_PIPE_AUX_TABLE_INVALIDATE_BIT)
/* PIPE_CONTROL bits that should be set only in 3D RCS mode.
* For more details see genX(emit_apply_pipe_flushes).
*/
#define ANV_PIPE_GFX_BITS ( \
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | \
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | \
ANV_PIPE_TILE_CACHE_FLUSH_BIT | \
ANV_PIPE_DEPTH_STALL_BIT | \
ANV_PIPE_STALL_AT_SCOREBOARD_BIT | \
(GFX_VERx10 >= 125 ? ANV_PIPE_PSS_STALL_SYNC_BIT : 0) | \
ANV_PIPE_VF_CACHE_INVALIDATE_BIT)
/* PIPE_CONTROL bits that should be set only in Media/GPGPU RCS mode.
* For more details see genX(emit_apply_pipe_flushes).
*/
#define ANV_PIPE_GPGPU_BITS ( \
(GFX_VERx10 >= 125 ? ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT : 0))
enum intel_ds_stall_flag
anv_pipe_flush_bit_to_ds_stall_flag(enum anv_pipe_bits bits);

43
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -1826,6 +1826,45 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
uint32_t current_pipeline,
enum anv_pipe_bits bits)
{
#if GFX_VER >= 12
/* From the TGL PRM, Volume 2a, "PIPE_CONTROL":
*
* "SW must follow below programming restrictions when programming
* PIPE_CONTROL command [for ComputeCS]:
* ...
* Following bits must not be set when programmed for ComputeCS:
* - "Render Target Cache Flush Enable", "Depth Cache Flush Enable"
* and "Tile Cache Flush Enable"
* - "Depth Stall Enable", Stall at Pixel Scoreboard and
* "PSD Sync Enable".
* - "OVR Tile 0 Flush", "TBIMR Force Batch Closure",
* "AMFS Flush Enable", "VF Cache Invalidation Enable" and
* "Global Snapshot Count Reset"."
*
* XXX: According to spec this should not be a concern for a regular
* RCS in GPGPU mode, but during testing it was found that at least
* "VF Cache Invalidation Enable" bit is ignored in such case.
* This can cause us to miss some important invalidations
* (e.g. from CmdPipelineBarriers) and have incoherent data.
*
* There is also a Wa_1606932921 "RCS is not waking up fixed function clock
* when specific 3d related bits are programmed in pipecontrol in
* compute mode" that suggests us not to use "RT Cache Flush" in GPGPU mode.
*
* The other bits are not confirmed to cause problems, but included here
* just to be safe, as they're also not really relevant in the GPGPU mode,
* and having them doesn't seem to cause any regressions.
*
* So if we're currently in GPGPU mode, we hide some bits from
* this flush, and will flush them only when we'll be able to.
* Similar thing with GPGPU-only bits.
*/
enum anv_pipe_bits defer_bits = bits &
(current_pipeline == GPGPU ? ANV_PIPE_GFX_BITS: ANV_PIPE_GPGPU_BITS);
bits &= ~defer_bits;
#endif
/*
* From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization":
*
@ -2089,6 +2128,10 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
bits &= ~ANV_PIPE_INVALIDATE_BITS;
}
#if GFX_VER >= 12
bits |= defer_bits;
#endif
return bits;
}