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i965: Implement WaCsStallAtEveryFourthPipecontrol on IVB/BYT.

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According to the documentation, we need to do a CS stall on every fourth
PIPE_CONTROL command to avoid GPU hangs.  The kernel does a CS stall
between batches, so we only need to count the PIPE_CONTROLs in our batches.

v2: Get the generation check right (caught by Chris Wilson),
    combine the ++ with the check (suggested by Daniel Vetter).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Kenneth Graunke 2014-11-12 11:17:55 -08:00
parent 3793a1b421
commit d41cf9fb60
2 changed files with 34 additions and 0 deletions
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2
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -868,6 +868,8 @@ struct intel_batchbuffer {
enum brw_gpu_ring ring;
bool needs_sol_reset;
uint8_t pipe_controls_since_last_cs_stall;
struct {
uint16_t used;
int reloc_count;

32
src/mesa/drivers/dri/i965/intel_batchbuffer.c
View file

@ -81,6 +81,7 @@ intel_batchbuffer_reset(struct brw_context *brw)
brw->batch.state_batch_offset = brw->batch.bo->size;
brw->batch.used = 0;
brw->batch.needs_sol_reset = false;
brw->batch.pipe_controls_since_last_cs_stall = 0;
/* We don't know what ring the new batch will be sent to until we see the
* first BEGIN_BATCH or BEGIN_BATCH_BLT. Mark it as unknown.
@ -433,6 +434,33 @@ gen8_add_cs_stall_workaround_bits(uint32_t *flags)
*flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
}
/* Implement the WaCsStallAtEveryFourthPipecontrol workaround on IVB, BYT:
*
* "Every 4th PIPE_CONTROL command, not counting the PIPE_CONTROL with
* only read-cache-invalidate bit(s) set, must have a CS_STALL bit set."
*
* Note that the kernel does CS stalls between batches, so we only need
* to count them within a batch.
*/
static uint32_t
gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw, uint32_t flags)
{
if (brw->gen == 7 && !brw->is_haswell) {
if (flags & PIPE_CONTROL_CS_STALL) {
/* If we're doing a CS stall, reset the counter and carry on. */
brw->batch.pipe_controls_since_last_cs_stall = 0;
return 0;
}
/* If this is the fourth pipe control without a CS stall, do one now. */
if (++brw->batch.pipe_controls_since_last_cs_stall == 4) {
brw->batch.pipe_controls_since_last_cs_stall = 0;
return PIPE_CONTROL_CS_STALL;
}
}
return 0;
}
/**
* Emit a PIPE_CONTROL with various flushing flags.
*
@ -454,6 +482,8 @@ brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags)
OUT_BATCH(0);
ADVANCE_BATCH();
} else if (brw->gen >= 6) {
flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
BEGIN_BATCH(5);
OUT_BATCH(_3DSTATE_PIPE_CONTROL | (5 - 2));
OUT_BATCH(flags);
@ -496,6 +526,8 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
OUT_BATCH(imm_upper);
ADVANCE_BATCH();
} else if (brw->gen >= 6) {
flags |= gen7_cs_stall_every_four_pipe_controls(brw, flags);
/* PPGTT/GGTT is selected by DW2 bit 2 on Sandybridge, but DW1 bit 24
* on later platforms. We always use PPGTT on Gen7+.
*/