fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-07 13:38:06 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

radv: Pass no_metadata_planes info in to ac_surface.

Browse source 
Also do not allocate aux surfaces for multi-plane images. I may
have messed up and used plane 1 offsets for the other planes as well.
I cannot imagine that sharing aux surfaces between the planes will
work well.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5194>
This commit is contained in:
Bas Nieuwenhuizen 2020-05-24 12:10:00 +02:00 • committed by Marge Bot
parent 599ea341dd
commit d3db633f6d
1 changed files with 36 additions and 35 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

71
src/amd/vulkan/radv_image.c
View file

@ -1374,6 +1374,12 @@ radv_image_create_layout(struct radv_device *device,
info.height /= desc->height_divisor; info.height /= desc->height_divisor;
} }
if (create_info.no_metadata_planes || image->plane_count > 1) {
image->planes[plane].surface.flags |= RADEON_SURF_DISABLE_DCC |
RADEON_SURF_NO_FMASK |
RADEON_SURF_NO_HTILE;
}
device->ws->surface_init(device->ws, &info, &image->planes[plane].surface); device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment); image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
@ -1383,44 +1389,39 @@ radv_image_create_layout(struct radv_device *device,
image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane); image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
} }
if (!create_info.no_metadata_planes) { /* Try to enable DCC first. */
/* Try to enable DCC first. */ if (radv_image_can_enable_dcc(device, image)) {
if (radv_image_can_enable_dcc(device, image)) { radv_image_alloc_dcc(image);
radv_image_alloc_dcc(image); if (image->info.samples > 1) {
if (image->info.samples > 1) { /* CMASK should be enabled because DCC fast
/* CMASK should be enabled because DCC fast * clear with MSAA needs it.
* clear with MSAA needs it. */
*/ assert(radv_image_can_enable_cmask(image));
assert(radv_image_can_enable_cmask(image)); radv_image_alloc_cmask(device, image);
radv_image_alloc_cmask(device, image);
}
} else {
/* When DCC cannot be enabled, try CMASK. */
radv_image_disable_dcc(image);
if (radv_image_can_enable_cmask(image)) {
radv_image_alloc_cmask(device, image);
}
}
/* Try to enable FMASK for multisampled images. */
if (image->planes[0].surface.fmask_size) {
radv_image_alloc_fmask(device, image);
if (radv_use_tc_compat_cmask_for_image(device, image))
image->tc_compatible_cmask = true;
} else {
/* Otherwise, try to enable HTILE for depth surfaces. */
if (radv_image_can_enable_htile(image) &&
!(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
radv_image_alloc_htile(device, image);
} else {
radv_image_disable_htile(image);
}
} }
} else { } else {
/* When DCC cannot be enabled, try CMASK. */
radv_image_disable_dcc(image); radv_image_disable_dcc(image);
radv_image_disable_htile(image); if (radv_image_can_enable_cmask(image)) {
radv_image_alloc_cmask(device, image);
}
}
/* Try to enable FMASK for multisampled images. */
if (image->planes[0].surface.fmask_size) {
radv_image_alloc_fmask(device, image);
if (radv_use_tc_compat_cmask_for_image(device, image))
image->tc_compatible_cmask = true;
} else {
/* Otherwise, try to enable HTILE for depth surfaces. */
if (radv_image_can_enable_htile(image) &&
!(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
radv_image_alloc_htile(device, image);
} else {
radv_image_disable_htile(image);
}
} }
assert(image->planes[0].surface.surf_size); assert(image->planes[0].surface.surf_size);