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radeonsi: add SI_IMAGE_ACCESS_DCC_OFF to ignore DCC for shader images

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A shader-based DCC decompress pass will use this.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761>
This commit is contained in:
Marek Olšák 2020-04-26 07:45:34 -04:00 • committed by Marge Bot
parent 93d5c86081
commit d3da73954a
4 changed files with 9 additions and 6 deletions
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10
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -279,7 +279,7 @@ static void si_set_buf_desc_address(struct si_resource *buf, uint64_t offset, ui
void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture *tex,
const struct legacy_surf_level *base_level_info,
unsigned base_level, unsigned first_level, unsigned block_width,
bool is_stencil, uint32_t *state)
bool is_stencil, bool force_dcc_off, uint32_t *state)
{
uint64_t va, meta_va = 0;
@ -313,7 +313,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture
if (sscreen->info.chip_class >= GFX8) {
state[6] &= C_008F28_COMPRESSION_EN;
if (vi_dcc_enabled(tex, first_level)) {
if (!force_dcc_off && vi_dcc_enabled(tex, first_level)) {
meta_va =
(!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) + tex->surface.dcc_offset;
@ -436,7 +436,7 @@ static void si_set_sampler_view_desc(struct si_context *sctx, struct si_sampler_
si_set_mutable_tex_desc_fields(sctx->screen, tex, sview->base_level_info, sview->base_level,
sview->base.u.tex.first_level, sview->block_width,
is_separate_stencil, desc);
is_separate_stencil, false, desc);
}
if (!is_buffer && tex->surface.fmask_size) {
@ -662,6 +662,7 @@ static void si_set_shader_image_desc(struct si_context *ctx, const struct pipe_i
assert(fmask_desc || tex->surface.fmask_offset == 0);
if (uses_dcc && !skip_decompress &&
!(access & SI_IMAGE_ACCESS_DCC_OFF) &&
(access & PIPE_IMAGE_ACCESS_WRITE ||
!vi_dcc_formats_compatible(screen, res->b.b.format, view->format))) {
/* If DCC can't be disabled, at least decompress it.
@ -697,7 +698,8 @@ static void si_set_shader_image_desc(struct si_context *ctx, const struct pipe_i
screen, tex, false, res->b.b.target, view->format, swizzle, hw_level, hw_level,
view->u.tex.first_layer, view->u.tex.last_layer, width, height, depth, desc, fmask_desc);
si_set_mutable_tex_desc_fields(screen, tex, &tex->surface.u.legacy.level[level], level, level,
util_format_get_blockwidth(view->format), false, desc);
util_format_get_blockwidth(view->format), false,
view->access & SI_IMAGE_ACCESS_DCC_OFF, desc);
}
}

1
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -134,6 +134,7 @@ enum si_clear_code
};
#define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
#define SI_IMAGE_ACCESS_DCC_OFF (1 << 8)
/* Debug flags. */
enum

2
src/gallium/drivers/radeonsi/si_state.h
View file

@ -485,7 +485,7 @@ struct si_buffer_resources {
void si_set_mutable_tex_desc_fields(struct si_screen *sscreen, struct si_texture *tex,
const struct legacy_surf_level *base_level_info,
unsigned base_level, unsigned first_level, unsigned block_width,
bool is_stencil, uint32_t *state);
bool is_stencil, bool force_dcc_off, uint32_t *state);
void si_update_ps_colorbuf0_slot(struct si_context *sctx);
void si_get_pipe_constant_buffer(struct si_context *sctx, uint shader, uint slot,
struct pipe_constant_buffer *cbuf);

2
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -661,7 +661,7 @@ static void si_set_tex_bo_metadata(struct si_screen *sscreen, struct si_texture
res->width0, res->height0, res->depth0, desc, NULL);
si_set_mutable_tex_desc_fields(sscreen, tex, &tex->surface.u.legacy.level[0], 0, 0,
tex->surface.blk_w, false, desc);
tex->surface.blk_w, false, false, desc);
/* Clear the base address and set the relative DCC offset. */
desc[0] = 0;