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i965/vec4/nir: remove emit_untyped_surface_read and emit_untyped_atomic at brw_vec4_visitor
surface_access emit_untyped_read and emit_untyped_atomic provides the same
functionality.
v2: surface parameter of emit_untyped_atomic is a const, no need to
specify default predicate on emit_untyped_atomic, use retype
(Francisco Jerez).
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
parent
0c5c2e2c93
commit
d3a89a7c49
3 changed files with 23 additions and 75 deletions
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@ -276,13 +276,6 @@ public:
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void emit_shader_time_end();
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void emit_shader_time_write(int shader_time_subindex, src_reg value);
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void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
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dst_reg dst, src_reg offset, src_reg src0,
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src_reg src1);
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void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
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src_reg offset);
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src_reg get_scratch_offset(bblock_t *block, vec4_instruction *inst,
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src_reg *reladdr, int reg_offset);
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src_reg get_pull_constant_offset(bblock_t *block, vec4_instruction *inst,
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@ -724,24 +724,34 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
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(unsigned) instr->const_index[0];
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src_reg offset = get_nir_src(instr->src[0], nir_type_int,
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instr->num_components);
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const src_reg surface = brw_imm_ud(surf_index);
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const vec4_builder bld =
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vec4_builder(this).at_end().annotate(current_annotation, base_ir);
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src_reg tmp;
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dest = get_nir_dest(instr->dest);
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switch (instr->intrinsic) {
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case nir_intrinsic_atomic_counter_inc:
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emit_untyped_atomic(BRW_AOP_INC, surf_index, dest, offset,
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src_reg(), src_reg());
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break;
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case nir_intrinsic_atomic_counter_dec:
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emit_untyped_atomic(BRW_AOP_PREDEC, surf_index, dest, offset,
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src_reg(), src_reg());
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break;
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case nir_intrinsic_atomic_counter_read:
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emit_untyped_surface_read(surf_index, dest, offset);
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break;
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default:
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unreachable("Unreachable");
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case nir_intrinsic_atomic_counter_inc:
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tmp = emit_untyped_atomic(bld, surface, offset,
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src_reg(), src_reg(),
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1, 1,
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BRW_AOP_INC);
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break;
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case nir_intrinsic_atomic_counter_dec:
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tmp = emit_untyped_atomic(bld, surface, offset,
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src_reg(), src_reg(),
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1, 1,
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BRW_AOP_PREDEC);
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break;
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case nir_intrinsic_atomic_counter_read:
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tmp = emit_untyped_read(bld, surface, offset, 1, 1);
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break;
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default:
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unreachable("Unreachable");
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}
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bld.MOV(retype(dest, tmp.type), tmp);
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brw_mark_surface_used(stage_prog_data, surf_index);
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break;
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}
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@ -1114,61 +1114,6 @@ vec4_visitor::gs_end_primitive()
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unreachable("not reached");
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}
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void
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vec4_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
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dst_reg dst, src_reg surf_offset,
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src_reg src0, src_reg src1)
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{
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unsigned mlen = 1 + (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
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src_reg src_payload(this, glsl_type::uint_type, mlen);
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dst_reg payload(src_payload);
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payload.writemask = WRITEMASK_X;
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/* Set the atomic operation offset. */
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emit(MOV(offset(payload, 0), surf_offset));
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unsigned i = 1;
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/* Set the atomic operation arguments. */
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if (src0.file != BAD_FILE) {
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emit(MOV(offset(payload, i), src0));
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i++;
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}
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if (src1.file != BAD_FILE) {
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emit(MOV(offset(payload, i), src1));
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i++;
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}
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/* Emit the instruction. Note that this maps to the normal SIMD8
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* untyped atomic message on Ivy Bridge, but that's OK because
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* unused channels will be masked out.
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*/
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vec4_instruction *inst = emit(SHADER_OPCODE_UNTYPED_ATOMIC, dst,
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src_payload,
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brw_imm_ud(surf_index), brw_imm_ud(atomic_op));
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inst->mlen = mlen;
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}
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void
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vec4_visitor::emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
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src_reg surf_offset)
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{
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dst_reg offset(this, glsl_type::uint_type);
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offset.writemask = WRITEMASK_X;
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/* Set the surface read offset. */
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emit(MOV(offset, surf_offset));
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/* Emit the instruction. Note that this maps to the normal SIMD8
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* untyped surface read message, but that's OK because unused
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* channels will be masked out.
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*/
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vec4_instruction *inst = emit(SHADER_OPCODE_UNTYPED_SURFACE_READ, dst,
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src_reg(offset),
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brw_imm_ud(surf_index), brw_imm_d(1));
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inst->mlen = 1;
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}
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void
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vec4_visitor::emit_ndc_computation()
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{
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