From d39bd7ba7050d6d31020ff6dee7fd99799e165df Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Fri, 4 Mar 2022 03:27:05 -0800 Subject: [PATCH] iris: Split out an IRIS_DOMAIN_SAMPLER_READ domain from OTHER_READ The bulk of IRIS_DOMAIN_OTHER_READ domain usage was the 3D sampler, but there were also a few oddball cases like command streamer reads, blitter access, and so on. The sampler is definitely L3 coherent, but some off the more esoteric reads may not be, so I'd like to separate them, so that OTHER_READ can become a non-L3-coherent kitchen-sink domain. The sampler cases only need TEXTURE_CACHE_INVALIDATE, and can skip the CONSTANT_CACHE_INVALIDATE we had on IRIS_DOMAIN_OTHER_READ. Reviewed-by: Francisco Jerez Reviewed-by: Rohan Garg Part-of: --- src/gallium/drivers/iris/iris_blit.c | 6 +++--- src/gallium/drivers/iris/iris_blorp.c | 2 +- src/gallium/drivers/iris/iris_bufmgr.h | 6 ++++-- src/gallium/drivers/iris/iris_pipe_control.c | 5 +++-- src/gallium/drivers/iris/iris_resolve.c | 2 +- src/gallium/drivers/iris/iris_state.c | 15 +++++++++------ 6 files changed, 21 insertions(+), 15 deletions(-) diff --git a/src/gallium/drivers/iris/iris_blit.c b/src/gallium/drivers/iris/iris_blit.c index 34b2e06cb35..3b32d65eeb1 100644 --- a/src/gallium/drivers/iris/iris_blit.c +++ b/src/gallium/drivers/iris/iris_blit.c @@ -499,7 +499,7 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) info->src.level, 1, info->src.box.z, info->src.box.depth); iris_emit_buffer_barrier_for(batch, src_res->bo, - IRIS_DOMAIN_OTHER_READ); + IRIS_DOMAIN_SAMPLER_READ); struct iris_format_info dst_fmt = iris_format_for_usage(devinfo, dst_pfmt, @@ -698,7 +698,7 @@ iris_copy_region(struct blorp_context *blorp, }; iris_emit_buffer_barrier_for(batch, src_res->bo, - IRIS_DOMAIN_OTHER_READ); + IRIS_DOMAIN_SAMPLER_READ); iris_emit_buffer_barrier_for(batch, dst_res->bo, write_domain); iris_batch_maybe_flush(batch, 1500); @@ -723,7 +723,7 @@ iris_copy_region(struct blorp_context *blorp, dst_aux_usage, dst_clear_supported); iris_emit_buffer_barrier_for(batch, src_res->bo, - IRIS_DOMAIN_OTHER_READ); + IRIS_DOMAIN_SAMPLER_READ); iris_emit_buffer_barrier_for(batch, dst_res->bo, write_domain); for (int slice = 0; slice < src_box->depth; slice++) { diff --git a/src/gallium/drivers/iris/iris_blorp.c b/src/gallium/drivers/iris/iris_blorp.c index 23f4710c93f..b54653846cb 100644 --- a/src/gallium/drivers/iris/iris_blorp.c +++ b/src/gallium/drivers/iris/iris_blorp.c @@ -400,7 +400,7 @@ iris_blorp_exec_render(struct blorp_batch *blorp_batch, if (params->src.enabled) iris_bo_bump_seqno(params->src.addr.buffer, batch->next_seqno, - IRIS_DOMAIN_OTHER_READ); + IRIS_DOMAIN_SAMPLER_READ); if (params->dst.enabled) iris_bo_bump_seqno(params->dst.addr.buffer, batch->next_seqno, IRIS_DOMAIN_RENDER_WRITE); diff --git a/src/gallium/drivers/iris/iris_bufmgr.h b/src/gallium/drivers/iris/iris_bufmgr.h index 9022cb504a6..77e8fd9aab6 100644 --- a/src/gallium/drivers/iris/iris_bufmgr.h +++ b/src/gallium/drivers/iris/iris_bufmgr.h @@ -111,6 +111,8 @@ enum iris_domain { IRIS_DOMAIN_OTHER_WRITE, /** Vertex cache. */ IRIS_DOMAIN_VF_READ, + /** Texture cache. */ + IRIS_DOMAIN_SAMPLER_READ, /** Any other read-only cache. */ IRIS_DOMAIN_OTHER_READ, /** Number of caching domains. */ @@ -125,8 +127,8 @@ enum iris_domain { static inline bool iris_domain_is_read_only(enum iris_domain access) { - return access == IRIS_DOMAIN_OTHER_READ || - access == IRIS_DOMAIN_VF_READ; + return access >= IRIS_DOMAIN_VF_READ && + access <= IRIS_DOMAIN_OTHER_READ; } enum iris_mmap_mode { diff --git a/src/gallium/drivers/iris/iris_pipe_control.c b/src/gallium/drivers/iris/iris_pipe_control.c index 5ef0acba396..a9b2bc538ff 100644 --- a/src/gallium/drivers/iris/iris_pipe_control.c +++ b/src/gallium/drivers/iris/iris_pipe_control.c @@ -193,6 +193,7 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch, [IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_DATA_CACHE_FLUSH, [IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE, [IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD, + [IRIS_DOMAIN_SAMPLER_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD, [IRIS_DOMAIN_OTHER_READ] = PIPE_CONTROL_STALL_AT_SCOREBOARD, }; const uint32_t invalidate_bits[NUM_IRIS_DOMAINS] = { @@ -201,8 +202,8 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch, [IRIS_DOMAIN_DATA_WRITE] = PIPE_CONTROL_DATA_CACHE_FLUSH, [IRIS_DOMAIN_OTHER_WRITE] = PIPE_CONTROL_FLUSH_ENABLE, [IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_VF_CACHE_INVALIDATE, - [IRIS_DOMAIN_OTHER_READ] = (PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | - PIPE_CONTROL_CONST_CACHE_INVALIDATE), + [IRIS_DOMAIN_SAMPLER_READ] = PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE, + [IRIS_DOMAIN_OTHER_READ] = PIPE_CONTROL_CONST_CACHE_INVALIDATE, }; uint32_t bits = 0; diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c index 1da1fff3b12..9296db3bffb 100644 --- a/src/gallium/drivers/iris/iris_resolve.c +++ b/src/gallium/drivers/iris/iris_resolve.c @@ -109,7 +109,7 @@ resolve_sampler_views(struct iris_context *ice, } iris_emit_buffer_barrier_for(batch, isv->res->bo, - IRIS_DOMAIN_OTHER_READ); + IRIS_DOMAIN_SAMPLER_READ); } } diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index aaa2f903a83..63a3d44b5fb 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -4992,15 +4992,15 @@ use_sampler_view(struct iris_context *ice, if (isv->res->aux.clear_color_bo) { iris_use_pinned_bo(batch, isv->res->aux.clear_color_bo, - false, IRIS_DOMAIN_OTHER_READ); + false, IRIS_DOMAIN_SAMPLER_READ); } if (isv->res->aux.bo) { iris_use_pinned_bo(batch, isv->res->aux.bo, - false, IRIS_DOMAIN_OTHER_READ); + false, IRIS_DOMAIN_SAMPLER_READ); } - iris_use_pinned_bo(batch, isv->res->bo, false, IRIS_DOMAIN_OTHER_READ); + iris_use_pinned_bo(batch, isv->res->bo, false, IRIS_DOMAIN_SAMPLER_READ); return use_surface_state(batch, &isv->surface_state, aux_usage); } @@ -5133,7 +5133,7 @@ iris_populate_binding_table(struct iris_context *ice, if (cso_fb->cbufs[i]) { addr = use_surface(ice, batch, cso_fb->cbufs[i], false, ice->state.draw_aux_usage[i], true, - IRIS_DOMAIN_OTHER_READ); + IRIS_DOMAIN_SAMPLER_READ); push_bt_entry(addr); } } @@ -7610,6 +7610,7 @@ batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags) if ((flags & (PIPE_CONTROL_CACHE_FLUSH_BITS | PIPE_CONTROL_STALL_AT_SCOREBOARD))) { iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_VF_READ); + iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_SAMPLER_READ); iris_batch_mark_flush_sync(batch, IRIS_DOMAIN_OTHER_READ); } } @@ -7629,8 +7630,10 @@ batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags) if ((flags & PIPE_CONTROL_VF_CACHE_INVALIDATE)) iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_VF_READ); - if ((flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE) && - (flags & PIPE_CONTROL_CONST_CACHE_INVALIDATE)) + if ((flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) + iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_SAMPLER_READ); + + if ((flags & PIPE_CONTROL_CONST_CACHE_INVALIDATE)) iris_batch_mark_invalidate_sync(batch, IRIS_DOMAIN_OTHER_READ); }