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https://gitlab.freedesktop.org/mesa/mesa.git
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svga: remove shader and compute get param
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33176>
This commit is contained in:
Qiang Yu
parent
b2c981183c
commit
d353965473
1 changed files with 0 additions and 305 deletions
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@ -131,256 +131,6 @@ get_bool_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
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return defaultVal;
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}
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static int
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vgpu9_get_shader_param(struct pipe_screen *screen,
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enum pipe_shader_type shader,
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enum pipe_shader_cap param)
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{
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struct svga_screen *svgascreen = svga_screen(screen);
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struct svga_winsys_screen *sws = svgascreen->sws;
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unsigned val;
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assert(!sws->have_vgpu10);
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switch (shader)
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{
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case PIPE_SHADER_FRAGMENT:
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switch (param)
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{
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case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
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case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
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return get_uint_cap(sws,
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SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
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512);
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case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
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case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
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return 512;
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case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
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return SVGA3D_MAX_NESTING_LEVEL;
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case PIPE_SHADER_CAP_MAX_INPUTS:
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return 10;
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case PIPE_SHADER_CAP_MAX_OUTPUTS:
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return svgascreen->max_color_buffers;
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case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
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return 224 * sizeof(float[4]);
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case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
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return 1;
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case PIPE_SHADER_CAP_MAX_TEMPS:
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val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
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return MIN2(val, SVGA3D_TEMPREG_MAX);
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case PIPE_SHADER_CAP_CONT_SUPPORTED:
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return 0;
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case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
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return 0;
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case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
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case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
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return 0;
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case PIPE_SHADER_CAP_SUBROUTINES:
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return 0;
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case PIPE_SHADER_CAP_INT64_ATOMICS:
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case PIPE_SHADER_CAP_INTEGERS:
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return 0;
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case PIPE_SHADER_CAP_FP16:
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case PIPE_SHADER_CAP_FP16_DERIVATIVES:
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case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
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case PIPE_SHADER_CAP_INT16:
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case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
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return 0;
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case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
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case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
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return 16;
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case PIPE_SHADER_CAP_SUPPORTED_IRS:
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return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
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case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
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case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
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case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
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case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
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case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
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return 0;
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}
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/* If we get here, we failed to handle a cap above */
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debug_printf("Unexpected fragment shader query %u\n", param);
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return 0;
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case PIPE_SHADER_VERTEX:
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switch (param)
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{
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case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
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case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
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return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
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512);
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case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
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case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
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/* XXX: until we have vertex texture support */
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return 0;
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case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
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return SVGA3D_MAX_NESTING_LEVEL;
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case PIPE_SHADER_CAP_MAX_INPUTS:
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return 16;
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case PIPE_SHADER_CAP_MAX_OUTPUTS:
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return 10;
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case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
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return 256 * sizeof(float[4]);
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case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
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return 1;
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case PIPE_SHADER_CAP_MAX_TEMPS:
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val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
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return MIN2(val, SVGA3D_TEMPREG_MAX);
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case PIPE_SHADER_CAP_CONT_SUPPORTED:
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return 0;
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case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
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return 0;
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case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
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return 0;
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case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
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return 1;
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case PIPE_SHADER_CAP_SUBROUTINES:
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return 0;
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case PIPE_SHADER_CAP_INT64_ATOMICS:
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case PIPE_SHADER_CAP_INTEGERS:
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return 0;
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case PIPE_SHADER_CAP_FP16:
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case PIPE_SHADER_CAP_FP16_DERIVATIVES:
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case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
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case PIPE_SHADER_CAP_INT16:
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case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
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return 0;
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case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
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case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
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return 0;
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case PIPE_SHADER_CAP_SUPPORTED_IRS:
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return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
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case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
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case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
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case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
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case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
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case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
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return 0;
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}
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/* If we get here, we failed to handle a cap above */
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debug_printf("Unexpected vertex shader query %u\n", param);
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return 0;
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case PIPE_SHADER_GEOMETRY:
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case PIPE_SHADER_COMPUTE:
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case PIPE_SHADER_TESS_CTRL:
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case PIPE_SHADER_TESS_EVAL:
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/* no support for geometry, tess or compute shaders at this time */
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return 0;
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case PIPE_SHADER_MESH:
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case PIPE_SHADER_TASK:
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return 0;
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default:
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debug_printf("Unexpected shader type (%u) query\n", shader);
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return 0;
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}
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return 0;
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}
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static int
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vgpu10_get_shader_param(struct pipe_screen *screen,
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enum pipe_shader_type shader,
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enum pipe_shader_cap param)
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{
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struct svga_screen *svgascreen = svga_screen(screen);
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struct svga_winsys_screen *sws = svgascreen->sws;
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assert(sws->have_vgpu10);
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(void) sws; /* silence unused var warnings in non-debug builds */
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if (shader == PIPE_SHADER_MESH || shader == PIPE_SHADER_TASK)
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return 0;
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if ((!sws->have_sm5) &&
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(shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL))
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return 0;
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if ((!sws->have_gl43) && (shader == PIPE_SHADER_COMPUTE))
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return 0;
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/* NOTE: we do not query the device for any caps/limits at this time */
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/* Generally the same limits for vertex, geometry and fragment shaders */
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switch (param) {
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case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
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case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
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case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
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case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
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return 64 * 1024;
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case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
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return 64;
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case PIPE_SHADER_CAP_MAX_INPUTS:
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if (shader == PIPE_SHADER_FRAGMENT)
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return VGPU10_MAX_PS_INPUTS;
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else if (shader == PIPE_SHADER_GEOMETRY)
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return svgascreen->max_gs_inputs;
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else if (shader == PIPE_SHADER_TESS_CTRL)
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return VGPU11_MAX_HS_INPUT_CONTROL_POINTS;
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else if (shader == PIPE_SHADER_TESS_EVAL)
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return VGPU11_MAX_DS_INPUT_CONTROL_POINTS;
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else
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return svgascreen->max_vs_inputs;
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case PIPE_SHADER_CAP_MAX_OUTPUTS:
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if (shader == PIPE_SHADER_FRAGMENT)
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return VGPU10_MAX_PS_OUTPUTS;
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else if (shader == PIPE_SHADER_GEOMETRY)
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return VGPU10_MAX_GS_OUTPUTS;
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else if (shader == PIPE_SHADER_TESS_CTRL)
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return VGPU11_MAX_HS_OUTPUTS;
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else if (shader == PIPE_SHADER_TESS_EVAL)
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return VGPU11_MAX_DS_OUTPUTS;
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else
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return svgascreen->max_vs_outputs;
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case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
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return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
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case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
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return svgascreen->max_const_buffers;
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case PIPE_SHADER_CAP_MAX_TEMPS:
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return VGPU10_MAX_TEMPS;
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case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
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case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
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return true; /* XXX verify */
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case PIPE_SHADER_CAP_CONT_SUPPORTED:
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case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
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case PIPE_SHADER_CAP_SUBROUTINES:
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case PIPE_SHADER_CAP_INTEGERS:
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return true;
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case PIPE_SHADER_CAP_FP16:
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case PIPE_SHADER_CAP_FP16_DERIVATIVES:
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case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
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case PIPE_SHADER_CAP_INT16:
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case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
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return false;
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case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
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case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
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return sws->have_gl43 ? PIPE_MAX_SAMPLERS : SVGA3D_DX_MAX_SAMPLERS;
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case PIPE_SHADER_CAP_SUPPORTED_IRS:
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if (sws->have_gl43)
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return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
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else
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return 0;
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case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
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return sws->have_gl43 ? SVGA_MAX_IMAGES : 0;
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case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
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return sws->have_gl43 ? SVGA_MAX_SHADER_BUFFERS : 0;
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case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
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case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
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return sws->have_gl43 ? SVGA_MAX_ATOMIC_BUFFERS : 0;
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case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
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case PIPE_SHADER_CAP_INT64_ATOMICS:
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return 0;
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default:
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debug_printf("Unexpected vgpu10 shader query %u\n", param);
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return 0;
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}
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return 0;
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}
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#define COMMON_OPTIONS \
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.lower_extract_byte = true, \
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.lower_extract_word = true, \
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@ -453,58 +203,6 @@ svga_get_compiler_options(struct pipe_screen *pscreen,
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}
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}
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static int
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svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
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enum pipe_shader_cap param)
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{
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struct svga_screen *svgascreen = svga_screen(screen);
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struct svga_winsys_screen *sws = svgascreen->sws;
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if (sws->have_vgpu10) {
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return vgpu10_get_shader_param(screen, shader, param);
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}
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else {
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return vgpu9_get_shader_param(screen, shader, param);
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}
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}
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static int
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svga_sm5_get_compute_param(struct pipe_screen *screen,
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enum pipe_compute_cap param,
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void *ret)
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{
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ASSERTED struct svga_screen *svgascreen = svga_screen(screen);
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ASSERTED struct svga_winsys_screen *sws = svgascreen->sws;
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uint64_t *iret = (uint64_t *)ret;
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assert(sws->have_gl43);
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switch (param) {
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case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
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iret[0] = 65535;
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iret[1] = 65535;
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iret[2] = 65535;
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return 3 * sizeof(uint64_t);
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case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
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iret[0] = 1024;
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iret[1] = 1024;
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iret[2] = 64;
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return 3 * sizeof(uint64_t);
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case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
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*iret = 1024;
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return sizeof(uint64_t);
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case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
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*iret = 32768;
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return sizeof(uint64_t);
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case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
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*iret = 0;
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return sizeof(uint64_t);
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default:
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debug_printf("Unexpected compute param %u\n", param);
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}
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return 0;
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}
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static void
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vgpu9_init_shader_caps(struct svga_screen *svgascreen)
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{
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@ -1093,7 +791,6 @@ svga_screen_create(struct svga_winsys_screen *sws)
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screen->get_vendor = svga_get_vendor;
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screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
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screen->get_screen_fd = svga_screen_get_fd;
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screen->get_shader_param = svga_get_shader_param;
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screen->get_compiler_options = svga_get_compiler_options;
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screen->get_timestamp = NULL;
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screen->is_format_supported = svga_is_format_supported;
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@ -1104,8 +801,6 @@ svga_screen_create(struct svga_winsys_screen *sws)
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screen->get_driver_query_info = svga_get_driver_query_info;
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screen->get_compute_param = svga_sm5_get_compute_param;
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svgascreen->sws = sws;
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svga_init_screen_resource_functions(svgascreen);
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