From d31cb824df23d374a275f2d89639f8aba5d51583 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Thu, 3 Jul 2025 10:57:28 -0400 Subject: [PATCH] treewide: use VARYING_BIT_* MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Via Coccinelle patch generated by the following Python: varys = [ "POS", "COL0", "COL1", "FOGC", "TEX0", "TEX1", "TEX2", "TEX3", "TEX4", "TEX5", "TEX6", "TEX7", "PSIZ", "BFC0", "BFC1", "EDGE", "CLIP_VERTEX", "CLIP_DIST0", "CLIP_DIST1", "CULL_DIST0", "CULL_DIST1", "PRIMITIVE_ID", "PRIMITIVE_COUNT", "LAYER", "VIEWPORT", "FACE", "PRIMITIVE_SHADING_RATE", "PNTC", "TESS_LEVEL_OUTER", "TESS_LEVEL_INNER", "PRIMITIVE_INDICES", "BOUNDING_BOX0", "BOUNDING_BOX1", "VIEWPORT_MASK", "CULL_PRIMITIVE" ] t = """ @@ @@ -(1 << VARYING_SLOT_${V}) +VARYING_BIT_${V} @@ @@ -BITFIELD_BIT(VARYING_SLOT_${V}) +VARYING_BIT_${V} @@ @@ -(1ull << VARYING_SLOT_${V}) +VARYING_BIT_${V} @@ @@ -BITFIELD64_BIT(VARYING_SLOT_${V}) +VARYING_BIT_${V} """ for v in varys: from mako.template import Template print(Template(t).render(V = v)) Closes: #13453 Signed-off-by: Alyssa Rosenzweig Reviewed-by: Faith Ekstrand Reviewed-by: Marek Olšák Reviewed-by: Erik Faye-Lund [panfrost, common] Reviewed-by: Alejandro Piñeiro [broadcom] Reviewed-by: Corentin Noël [virgl] Acked-by: Mike Blumenkrantz [zink] Part-of: --- src/amd/common/nir/ac_nir_lower_legacy_vs.c | 2 +- src/amd/common/nir/ac_nir_lower_ngg.c | 2 +- src/amd/common/nir/ac_nir_lower_ngg_mesh.c | 24 +++++++++---------- .../vulkan/nir/radv_nir_export_multiview.c | 2 +- src/amd/vulkan/radv_pipeline_graphics.c | 2 +- src/amd/vulkan/radv_shader.c | 2 +- src/amd/vulkan/radv_shader_info.c | 6 ++--- src/broadcom/compiler/vir.c | 4 ++-- src/broadcom/vulkan/v3dv_meta_clear.c | 5 ++-- src/broadcom/vulkan/v3dv_meta_copy.c | 6 ++--- src/broadcom/vulkan/v3dv_pipeline.c | 7 +++--- .../nir/nir_io_add_const_offset_to_base.c | 2 +- src/compiler/nir/nir_lower_texcoord_replace.c | 2 +- .../nir/nir_lower_texcoord_replace_late.c | 2 +- src/freedreno/vulkan/tu_shader.cc | 2 +- src/gallium/auxiliary/nir/tgsi_to_nir.c | 2 +- src/gallium/drivers/crocus/crocus_program.c | 16 ++++++------- .../drivers/radeonsi/si_nir_kill_outputs.c | 2 +- src/gallium/drivers/radeonsi/si_shader_nir.c | 2 +- src/gallium/drivers/virgl/virgl_context.c | 10 ++++---- .../drivers/zink/nir_to_spirv/nir_to_spirv.c | 16 ++++++------- src/intel/compiler/brw_nir.c | 4 ++-- src/intel/compiler/brw_nir_wa_18019110168.c | 14 +++++------ src/intel/compiler/elk/elk_fs.cpp | 2 +- src/intel/compiler/elk/elk_vue_map.c | 16 ++++++------- src/mesa/state_tracker/st_util.h | 4 ++-- src/panfrost/compiler/bifrost_compile.c | 10 ++++---- src/panfrost/lib/pan_shader.c | 10 ++++---- 28 files changed, 86 insertions(+), 92 deletions(-) diff --git a/src/amd/common/nir/ac_nir_lower_legacy_vs.c b/src/amd/common/nir/ac_nir_lower_legacy_vs.c index 4b6e51dbfff..4b8aa96bde1 100644 --- a/src/amd/common/nir/ac_nir_lower_legacy_vs.c +++ b/src/amd/common/nir/ac_nir_lower_legacy_vs.c @@ -61,7 +61,7 @@ ac_nir_lower_legacy_vs(nir_shader *nir, out.infos[VARYING_SLOT_PRIMITIVE_ID].as_varying_mask = 0x1; /* Update outputs_written to reflect that the pass added a new output. */ - nir->info.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_ID); + nir->info.outputs_written |= VARYING_BIT_PRIMITIVE_ID; } if (!disable_streamout && nir->xfb_info) diff --git a/src/amd/common/nir/ac_nir_lower_ngg.c b/src/amd/common/nir/ac_nir_lower_ngg.c index aeeb6a602f8..6152cb35446 100644 --- a/src/amd/common/nir/ac_nir_lower_ngg.c +++ b/src/amd/common/nir/ac_nir_lower_ngg.c @@ -884,7 +884,7 @@ clipdist_culling_es_part(nir_builder *b, lower_ngg_nogs_state *s, if (s->options->cull_clipdist_mask && !s->has_clipdist) { /* use gl_ClipVertex if defined */ nir_variable *clip_vertex_var = - b->shader->info.outputs_written & BITFIELD64_BIT(VARYING_SLOT_CLIP_VERTEX) ? + b->shader->info.outputs_written & VARYING_BIT_CLIP_VERTEX ? s->clip_vertex_var : s->position_value_var; nir_def *clip_vertex = nir_load_var(b, clip_vertex_var); diff --git a/src/amd/common/nir/ac_nir_lower_ngg_mesh.c b/src/amd/common/nir/ac_nir_lower_ngg_mesh.c index a6c212a2965..76e2201f5b9 100644 --- a/src/amd/common/nir/ac_nir_lower_ngg_mesh.c +++ b/src/amd/common/nir/ac_nir_lower_ngg_mesh.c @@ -11,9 +11,9 @@ #include "nir_builder.h" #define SPECIAL_MS_OUT_MASK \ - (BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_COUNT) | \ - BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES) | \ - BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE)) + (VARYING_BIT_PRIMITIVE_COUNT | \ + VARYING_BIT_PRIMITIVE_INDICES | \ + VARYING_BIT_CULL_PRIMITIVE) #define MS_PRIM_ARG_EXP_MASK \ (VARYING_BIT_LAYER | \ @@ -143,7 +143,7 @@ ms_store_prim_indices(nir_builder *b, if (store_val->num_components > s->vertices_per_prim) store_val = nir_trim_vector(b, store_val, s->vertices_per_prim); - if (s->layout.var.prm_attr.mask & BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES)) { + if (s->layout.var.prm_attr.mask & VARYING_BIT_PRIMITIVE_INDICES) { for (unsigned c = 0; c < store_val->num_components; ++c) { const unsigned i = VARYING_SLOT_PRIMITIVE_INDICES * 4 + c + component_offset; nir_store_var(b, s->out_variables[i], nir_channel(b, store_val, c), 0x1); @@ -176,7 +176,7 @@ ms_store_cull_flag(nir_builder *b, assert(store_val->num_components == 1); assert(store_val->bit_size == 1); - if (s->layout.var.prm_attr.mask & BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE)) { + if (s->layout.var.prm_attr.mask & VARYING_BIT_CULL_PRIMITIVE) { nir_store_var(b, s->out_variables[VARYING_SLOT_CULL_PRIMITIVE * 4], nir_b2i32(b, store_val), 0x1); return; } @@ -768,7 +768,7 @@ ms_prim_exp_arg_ch1(nir_builder *b, nir_def *invocation_index, nir_def *num_vtx, nir_def *indices_loaded = NULL; nir_def *cull_flag = NULL; - if (s->layout.var.prm_attr.mask & BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES)) { + if (s->layout.var.prm_attr.mask & VARYING_BIT_PRIMITIVE_INDICES) { nir_def *indices[3] = {0}; for (unsigned c = 0; c < s->vertices_per_prim; ++c) indices[c] = nir_load_var(b, s->out_variables[VARYING_SLOT_PRIMITIVE_INDICES * 4 + c]); @@ -780,7 +780,7 @@ ms_prim_exp_arg_ch1(nir_builder *b, nir_def *invocation_index, nir_def *num_vtx, if (s->uses_cull_flags) { nir_def *loaded_cull_flag = NULL; - if (s->layout.var.prm_attr.mask & BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE)) + if (s->layout.var.prm_attr.mask & VARYING_BIT_CULL_PRIMITIVE) loaded_cull_flag = nir_load_var(b, s->out_variables[VARYING_SLOT_CULL_PRIMITIVE * 4]); else loaded_cull_flag = nir_u2u32(b, nir_load_shared(b, 1, 8, prim_idx_addr, .base = s->layout.lds.cull_flags_addr)); @@ -1246,8 +1246,8 @@ ms_calculate_output_layout(const struct radeon_info *hw_info, unsigned api_share VARYING_BIT_POS | VARYING_BIT_CULL_DIST0 | VARYING_BIT_CULL_DIST1 | VARYING_BIT_CLIP_DIST0 | VARYING_BIT_CLIP_DIST1 | VARYING_BIT_PSIZ | VARYING_BIT_VIEWPORT | VARYING_BIT_PRIMITIVE_SHADING_RATE | VARYING_BIT_LAYER | - BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_COUNT) | - BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES) | BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE); + VARYING_BIT_PRIMITIVE_COUNT | + VARYING_BIT_PRIMITIVE_INDICES | VARYING_BIT_CULL_PRIMITIVE; const bool use_attr_ring = hw_info->has_attr_ring; const uint64_t attr_ring_per_vertex_output_mask = @@ -1263,9 +1263,9 @@ ms_calculate_output_layout(const struct radeon_info *hw_info, unsigned api_share cross_invocation_output_access & ~SPECIAL_MS_OUT_MASK; const bool cross_invocation_indices = - cross_invocation_output_access & BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES); + cross_invocation_output_access & VARYING_BIT_PRIMITIVE_INDICES; const bool cross_invocation_cull_primitive = - cross_invocation_output_access & BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE); + cross_invocation_output_access & VARYING_BIT_CULL_PRIMITIVE; /* Shared memory used by the API shader. */ ms_out_mem_layout l = { .lds = { .total_size = api_shared_size } }; @@ -1354,7 +1354,7 @@ ac_nir_lower_ngg_mesh(nir_shader *shader, shader->info.per_primitive_outputs & shader->info.outputs_written; /* Whether the shader uses CullPrimitiveEXT */ - bool uses_cull = shader->info.outputs_written & BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE); + bool uses_cull = shader->info.outputs_written & VARYING_BIT_CULL_PRIMITIVE; /* Can't handle indirect register addressing, pretend as if they were cross-invocation. */ uint64_t cross_invocation_access = shader->info.mesh.ms_cross_invocation_output_access | (shader->info.outputs_read_indirectly | diff --git a/src/amd/vulkan/nir/radv_nir_export_multiview.c b/src/amd/vulkan/nir/radv_nir_export_multiview.c index bb67d0f0514..97f59dfb37c 100644 --- a/src/amd/vulkan/nir/radv_nir_export_multiview.c +++ b/src/amd/vulkan/nir/radv_nir_export_multiview.c @@ -72,7 +72,7 @@ radv_nir_export_multiview(nir_shader *nir) nir_store_var(&b, layer, nir_load_view_index(&b), 1); /* Update outputs_written to reflect that the pass added a new output. */ - nir->info.outputs_written |= BITFIELD64_BIT(VARYING_SLOT_LAYER); + nir->info.outputs_written |= VARYING_BIT_LAYER; progress = true; if (nir->info.stage == MESA_SHADER_VERTEX) diff --git a/src/amd/vulkan/radv_pipeline_graphics.c b/src/amd/vulkan/radv_pipeline_graphics.c index 8e7db05cef8..7d80bdf24fd 100644 --- a/src/amd/vulkan/radv_pipeline_graphics.c +++ b/src/amd/vulkan/radv_pipeline_graphics.c @@ -2129,7 +2129,7 @@ radv_consider_force_vrs(const struct radv_graphics_state_key *gfx_state, const s if (last_vgt_stage->info.stage == MESA_SHADER_MESH) return false; - if (last_vgt_stage->nir->info.outputs_written & BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_SHADING_RATE)) + if (last_vgt_stage->nir->info.outputs_written & VARYING_BIT_PRIMITIVE_SHADING_RATE) return false; /* VRS has no effect if there is no pixel shader. */ diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index b8ec1d59009..cb623339bfd 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -662,7 +662,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st /* Lower primitive shading rate to match HW requirements. */ if ((nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_GEOMETRY || nir->info.stage == MESA_SHADER_MESH) && - nir->info.outputs_written & BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_SHADING_RATE)) { + nir->info.outputs_written & VARYING_BIT_PRIMITIVE_SHADING_RATE) { /* Lower primitive shading rate to match HW requirements. */ NIR_PASS(_, nir, radv_nir_lower_primitive_shading_rate, pdev->info.gfx_level); } diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index 8e69c66844d..d772a2818fd 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -406,9 +406,9 @@ radv_get_output_masks(const struct nir_shader *nir, const struct radv_graphics_s uint64_t *per_vtx_mask, uint64_t *per_prim_mask) { /* These are not compiled into neither output param nor position exports. */ - const uint64_t special_mask = BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_COUNT) | - BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES) | - BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE); + const uint64_t special_mask = VARYING_BIT_PRIMITIVE_COUNT | + VARYING_BIT_PRIMITIVE_INDICES | + VARYING_BIT_CULL_PRIMITIVE; *per_prim_mask = nir->info.outputs_written & nir->info.per_primitive_outputs & ~special_mask; *per_vtx_mask = nir->info.outputs_written & ~nir->info.per_primitive_outputs & ~special_mask; diff --git a/src/broadcom/compiler/vir.c b/src/broadcom/compiler/vir.c index 9a53669f50a..d289f8f71d1 100644 --- a/src/broadcom/compiler/vir.c +++ b/src/broadcom/compiler/vir.c @@ -826,7 +826,7 @@ v3d_vs_set_prog_data(struct v3d_compile *c, prog_data->vpm_input_size++; prog_data->writes_psiz = - c->s->info.outputs_written & (1 << VARYING_SLOT_PSIZ); + c->s->info.outputs_written & VARYING_BIT_PSIZ; /* Input/output segment size are in sectors (8 rows of 32 bits per * channel). @@ -905,7 +905,7 @@ v3d_gs_set_prog_data(struct v3d_compile *c, prog_data->num_invocations = c->s->info.gs.invocations; prog_data->writes_psiz = - c->s->info.outputs_written & (1 << VARYING_SLOT_PSIZ); + c->s->info.outputs_written & VARYING_BIT_PSIZ; } static void diff --git a/src/broadcom/vulkan/v3dv_meta_clear.c b/src/broadcom/vulkan/v3dv_meta_clear.c index 926f5eb8544..f041de91239 100644 --- a/src/broadcom/vulkan/v3dv_meta_clear.c +++ b/src/broadcom/vulkan/v3dv_meta_clear.c @@ -355,9 +355,8 @@ get_clear_rect_gs(const nir_shader_compiler_options *options, nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_GEOMETRY, options, "meta clear gs"); nir_shader *nir = b.shader; - nir->info.inputs_read = 1ull << VARYING_SLOT_POS; - nir->info.outputs_written = (1ull << VARYING_SLOT_POS) | - (1ull << VARYING_SLOT_LAYER); + nir->info.inputs_read = VARYING_BIT_POS; + nir->info.outputs_written = VARYING_BIT_POS | VARYING_BIT_LAYER; nir->info.gs.input_primitive = MESA_PRIM_TRIANGLES; nir->info.gs.output_primitive = MESA_PRIM_TRIANGLE_STRIP; nir->info.gs.vertices_in = 3; diff --git a/src/broadcom/vulkan/v3dv_meta_copy.c b/src/broadcom/vulkan/v3dv_meta_copy.c index 673cdca9f99..a3902420064 100644 --- a/src/broadcom/vulkan/v3dv_meta_copy.c +++ b/src/broadcom/vulkan/v3dv_meta_copy.c @@ -2240,9 +2240,9 @@ get_texel_buffer_copy_gs(const nir_shader_compiler_options *options) nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_GEOMETRY, options, "meta texel buffer copy gs"); nir_shader *nir = b.shader; - nir->info.inputs_read = 1ull << VARYING_SLOT_POS; - nir->info.outputs_written = (1ull << VARYING_SLOT_POS) | - (1ull << VARYING_SLOT_LAYER); + nir->info.inputs_read = VARYING_BIT_POS; + nir->info.outputs_written = VARYING_BIT_POS | + VARYING_BIT_LAYER; nir->info.gs.input_primitive = MESA_PRIM_TRIANGLES; nir->info.gs.output_primitive = MESA_PRIM_TRIANGLE_STRIP; nir->info.gs.vertices_in = 3; diff --git a/src/broadcom/vulkan/v3dv_pipeline.c b/src/broadcom/vulkan/v3dv_pipeline.c index 8fbe8abf282..d04a6beab04 100644 --- a/src/broadcom/vulkan/v3dv_pipeline.c +++ b/src/broadcom/vulkan/v3dv_pipeline.c @@ -1297,7 +1297,7 @@ pipeline_populate_v3d_gs_key(struct v3d_gs_key *key, struct v3dv_pipeline *pipeline = p_stage->pipeline; key->per_vertex_point_size = - p_stage->nir->info.outputs_written & (1ull << VARYING_SLOT_PSIZ); + p_stage->nir->info.outputs_written & VARYING_BIT_PSIZ; key->is_coord = broadcom_shader_stage_is_binning(p_stage->stage); @@ -1340,7 +1340,7 @@ pipeline_populate_v3d_vs_key(struct v3d_vs_key *key, struct v3dv_pipeline *pipeline = p_stage->pipeline; key->per_vertex_point_size = - p_stage->nir->info.outputs_written & (1ull << VARYING_SLOT_PSIZ); + p_stage->nir->info.outputs_written & VARYING_BIT_PSIZ; key->is_coord = broadcom_shader_stage_is_binning(p_stage->stage); @@ -2295,8 +2295,7 @@ pipeline_add_multiview_gs(struct v3dv_pipeline *pipeline, "multiview broadcast gs"); nir_shader *nir = b.shader; nir->info.inputs_read = vs_nir->info.outputs_written; - nir->info.outputs_written = vs_nir->info.outputs_written | - (1ull << VARYING_SLOT_LAYER); + nir->info.outputs_written = vs_nir->info.outputs_written | VARYING_BIT_LAYER; uint32_t vertex_count = mesa_vertices_per_prim(pipeline->topology); nir->info.gs.input_primitive = diff --git a/src/compiler/nir/nir_io_add_const_offset_to_base.c b/src/compiler/nir/nir_io_add_const_offset_to_base.c index f8a0b6d3517..7bc49cd03a0 100644 --- a/src/compiler/nir/nir_io_add_const_offset_to_base.c +++ b/src/compiler/nir/nir_io_add_const_offset_to_base.c @@ -91,7 +91,7 @@ add_const_offset_to_base_block(nir_block *block, nir_builder *b, if (b->shader->info.stage == MESA_SHADER_MESH && sem.location == VARYING_SLOT_PRIMITIVE_INDICES && !(b->shader->info.per_primitive_outputs & - BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES))) + VARYING_BIT_PRIMITIVE_INDICES)) continue; nir_src *offset = nir_get_io_offset_src(intrin); diff --git a/src/compiler/nir/nir_lower_texcoord_replace.c b/src/compiler/nir/nir_lower_texcoord_replace.c index 850138db575..7a79cb2a705 100644 --- a/src/compiler/nir/nir_lower_texcoord_replace.c +++ b/src/compiler/nir/nir_lower_texcoord_replace.c @@ -74,7 +74,7 @@ nir_lower_texcoord_replace_impl(nir_function_impl *impl, /* find or create pntc */ nir_variable *pntc = nir_get_variable_with_location(b.shader, nir_var_shader_in, VARYING_SLOT_PNTC, glsl_vec_type(2)); - b.shader->info.inputs_read |= BITFIELD64_BIT(VARYING_SLOT_PNTC); + b.shader->info.inputs_read |= VARYING_BIT_PNTC; new_coord = nir_load_var(&b, pntc); } diff --git a/src/compiler/nir/nir_lower_texcoord_replace_late.c b/src/compiler/nir/nir_lower_texcoord_replace_late.c index ee470a5606e..e5e672879d8 100644 --- a/src/compiler/nir/nir_lower_texcoord_replace_late.c +++ b/src/compiler/nir/nir_lower_texcoord_replace_late.c @@ -86,7 +86,7 @@ nir_lower_texcoord_replace_late(nir_shader *s, unsigned coord_replace, s->info.inputs_read &= ~(((uint64_t)coord_replace) << VARYING_SLOT_TEX0); if (!point_coord_is_sysval) - s->info.inputs_read |= BITFIELD64_BIT(VARYING_SLOT_PNTC); + s->info.inputs_read |= VARYING_BIT_PNTC; return nir_shader_instructions_pass(s, pass, nir_metadata_control_flow, diff --git a/src/freedreno/vulkan/tu_shader.cc b/src/freedreno/vulkan/tu_shader.cc index 17f7b610721..f9af424f5f9 100644 --- a/src/freedreno/vulkan/tu_shader.cc +++ b/src/freedreno/vulkan/tu_shader.cc @@ -3002,7 +3002,7 @@ tu_compile_shaders(struct tu_device *device, if (stage > MESA_SHADER_TESS_CTRL) { if (stage == MESA_SHADER_FRAGMENT) { ir3_key.tcs_store_primid = ir3_key.tcs_store_primid || - (nir[stage]->info.inputs_read & (1ull << VARYING_SLOT_PRIMITIVE_ID)); + (nir[stage]->info.inputs_read & VARYING_BIT_PRIMITIVE_ID); } else { ir3_key.tcs_store_primid = ir3_key.tcs_store_primid || BITSET_TEST(nir[stage]->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID); diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c index 7d7b6727755..e87d6dcd15a 100644 --- a/src/gallium/auxiliary/nir/tgsi_to_nir.c +++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c @@ -2551,7 +2551,7 @@ ttn_finalize_nir(struct ttn_compile *c, struct pipe_screen *screen) /* driver needs clipdistance as array */ if ((nir->info.outputs_written & - (BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST0) | BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST1))) && + (VARYING_BIT_CLIP_DIST0 | VARYING_BIT_CLIP_DIST1)) && nir->options->compact_arrays) { NIR_PASS(_, nir, lower_clipdistance_to_array); } diff --git a/src/gallium/drivers/crocus/crocus_program.c b/src/gallium/drivers/crocus/crocus_program.c index 22f36c8bdf2..663296b2ef0 100644 --- a/src/gallium/drivers/crocus/crocus_program.c +++ b/src/gallium/drivers/crocus/crocus_program.c @@ -1093,7 +1093,7 @@ crocus_vs_outputs_written(struct crocus_context *ice, if (devinfo->ver < 6) { if (key->copy_edgeflag) - outputs_written |= BITFIELD64_BIT(VARYING_SLOT_EDGE); + outputs_written |= VARYING_BIT_EDGE; /* Put dummy slots into the VUE for the SF to put the replaced * point sprite coords in. We shouldn't need these dummy slots, @@ -1107,10 +1107,10 @@ crocus_vs_outputs_written(struct crocus_context *ice, } /* if back colors are written, allocate slots for front colors too */ - if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_BFC0)) - outputs_written |= BITFIELD64_BIT(VARYING_SLOT_COL0); - if (outputs_written & BITFIELD64_BIT(VARYING_SLOT_BFC1)) - outputs_written |= BITFIELD64_BIT(VARYING_SLOT_COL1); + if (outputs_written & VARYING_BIT_BFC0) + outputs_written |= VARYING_BIT_COL0; + if (outputs_written & VARYING_BIT_BFC1) + outputs_written |= VARYING_BIT_COL1; } /* In order for legacy clipping to work, we need to populate the clip @@ -1118,8 +1118,8 @@ crocus_vs_outputs_written(struct crocus_context *ice, * shader doesn't write to gl_ClipDistance. */ if (key->nr_userclip_plane_consts > 0) { - outputs_written |= BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST0); - outputs_written |= BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST1); + outputs_written |= VARYING_BIT_CLIP_DIST0; + outputs_written |= VARYING_BIT_CLIP_DIST1; } return outputs_written; @@ -2220,7 +2220,7 @@ crocus_update_compiled_sf(struct crocus_context *ice) switch (ice->state.reduced_prim_mode) { case MESA_PRIM_TRIANGLES: default: - if (key.attrs & BITFIELD64_BIT(VARYING_SLOT_EDGE)) + if (key.attrs & VARYING_BIT_EDGE) key.primitive = ELK_SF_PRIM_UNFILLED_TRIS; else key.primitive = ELK_SF_PRIM_TRIANGLES; diff --git a/src/gallium/drivers/radeonsi/si_nir_kill_outputs.c b/src/gallium/drivers/radeonsi/si_nir_kill_outputs.c index 2953f568b99..1496924f3a0 100644 --- a/src/gallium/drivers/radeonsi/si_nir_kill_outputs.c +++ b/src/gallium/drivers/radeonsi/si_nir_kill_outputs.c @@ -15,7 +15,7 @@ bool si_nir_kill_outputs(nir_shader *nir, const union si_shader_key *key) !key->ge.opt.kill_pointsize && !key->ge.opt.kill_layer && !key->ge.opt.kill_clip_distances && - !(nir->info.outputs_written & BITFIELD64_BIT(VARYING_SLOT_LAYER)) && + !(nir->info.outputs_written & VARYING_BIT_LAYER) && !key->ge.opt.remove_streamout && !key->ge.mono.remove_streamout) { return nir_no_progress(impl); diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c index e45a65e3e58..57199d03675 100644 --- a/src/gallium/drivers/radeonsi/si_shader_nir.c +++ b/src/gallium/drivers/radeonsi/si_shader_nir.c @@ -244,7 +244,7 @@ void si_lower_mediump_io(nir_shader *nir) * dEQP-GLES31.functional.shaders.builtin_functions.integer.bitfieldinsert.uvec3_lowp_geometry */ (nir->info.stage != MESA_SHADER_VERTEX ? nir_var_shader_in : 0) | nir_var_shader_out, - BITFIELD64_BIT(VARYING_SLOT_PNTC) | BITFIELD64_RANGE(VARYING_SLOT_VAR0, 32), + VARYING_BIT_PNTC | BITFIELD64_RANGE(VARYING_SLOT_VAR0, 32), true); } diff --git a/src/gallium/drivers/virgl/virgl_context.c b/src/gallium/drivers/virgl/virgl_context.c index b0c24c1cd9e..61d23d19535 100644 --- a/src/gallium/drivers/virgl/virgl_context.c +++ b/src/gallium/drivers/virgl/virgl_context.c @@ -725,12 +725,10 @@ static void *virgl_shader_encoder(struct pipe_context *ctx, * more than 32 IO locations explicitly, and with varyings and patches we already * exhaust the possible ways of handling this for the varyings with generic names, * so drop the flag in these cases */ - const uint64_t drop_slots_for_separable_io = 0xffull << VARYING_SLOT_TEX0 | - 1 << VARYING_SLOT_FOGC | - 1 << VARYING_SLOT_BFC0 | - 1 << VARYING_SLOT_BFC1 | - 1 << VARYING_SLOT_COL0 | - 1 << VARYING_SLOT_COL1; + const uint64_t drop_slots_for_separable_io = + VARYING_BITS_TEX_ANY | VARYING_BIT_FOGC | VARYING_BIT_BFC0 | + VARYING_BIT_BFC1 | VARYING_BIT_COL0 | VARYING_BIT_COL1; + bool keep_separable_flags = true; if (s->info.stage != MESA_SHADER_VERTEX) keep_separable_flags &= !(s->info.inputs_read & drop_slots_for_separable_io); diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c index 246a552a6e5..0df38536fb5 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c +++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c @@ -4657,13 +4657,13 @@ nir_to_spirv(struct nir_shader *s, const struct zink_shader_info *sinfo, const s case MESA_SHADER_TESS_EVAL: spirv_builder_emit_cap(&ctx.builder, SpvCapabilityTessellation); /* TODO: check features for this */ - if (s->info.outputs_written & BITFIELD64_BIT(VARYING_SLOT_PSIZ)) + if (s->info.outputs_written & VARYING_BIT_PSIZ) spirv_builder_emit_cap(&ctx.builder, SpvCapabilityTessellationPointSize); break; case MESA_SHADER_GEOMETRY: spirv_builder_emit_cap(&ctx.builder, SpvCapabilityGeometry); - if (s->info.outputs_written & BITFIELD64_BIT(VARYING_SLOT_PSIZ)) + if (s->info.outputs_written & VARYING_BIT_PSIZ) spirv_builder_emit_cap(&ctx.builder, SpvCapabilityGeometryPointSize); break; @@ -4671,8 +4671,8 @@ nir_to_spirv(struct nir_shader *s, const struct zink_shader_info *sinfo, const s } if (s->info.stage < MESA_SHADER_GEOMETRY) { - if (s->info.outputs_written & BITFIELD64_BIT(VARYING_SLOT_LAYER) || - s->info.inputs_read & BITFIELD64_BIT(VARYING_SLOT_LAYER)) { + if (s->info.outputs_written & VARYING_BIT_LAYER || + s->info.inputs_read & VARYING_BIT_LAYER) { if (spirv_version >= SPIRV_VERSION(1, 5)) spirv_builder_emit_cap(&ctx.builder, SpvCapabilityShaderLayer); else { @@ -4684,8 +4684,8 @@ nir_to_spirv(struct nir_shader *s, const struct zink_shader_info *sinfo, const s /* incredibly, this is legal and intended. * https://github.com/KhronosGroup/SPIRV-Registry/issues/95 */ - if (s->info.inputs_read & (BITFIELD64_BIT(VARYING_SLOT_LAYER) | - BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_ID))) + if (s->info.inputs_read & (VARYING_BIT_LAYER | + VARYING_BIT_PRIMITIVE_ID)) spirv_builder_emit_cap(&ctx.builder, SpvCapabilityGeometry); } @@ -4693,7 +4693,7 @@ nir_to_spirv(struct nir_shader *s, const struct zink_shader_info *sinfo, const s spirv_builder_emit_extension(&ctx.builder, "SPV_KHR_storage_buffer_storage_class"); if (s->info.stage < MESA_SHADER_FRAGMENT && - s->info.outputs_written & BITFIELD64_BIT(VARYING_SLOT_VIEWPORT)) { + s->info.outputs_written & VARYING_BIT_VIEWPORT) { if (s->info.stage < MESA_SHADER_GEOMETRY) spirv_builder_emit_cap(&ctx.builder, SpvCapabilityShaderViewportIndex); else @@ -4701,7 +4701,7 @@ nir_to_spirv(struct nir_shader *s, const struct zink_shader_info *sinfo, const s } if (s->info.stage > MESA_SHADER_VERTEX && - s->info.inputs_read & BITFIELD64_BIT(VARYING_SLOT_VIEWPORT)) { + s->info.inputs_read & VARYING_BIT_VIEWPORT) { if (s->info.stage < MESA_SHADER_GEOMETRY) spirv_builder_emit_cap(&ctx.builder, SpvCapabilityShaderViewportIndex); else diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index bf332829cc4..65e3f5253e7 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -1526,8 +1526,8 @@ brw_nir_link_shaders(const struct brw_compiler *compiler, ms_outputs |= BITFIELD64_BIT(var->data.location); uint64_t zero_inputs = ~ms_outputs & fs_inputs; - zero_inputs &= BITFIELD64_BIT(VARYING_SLOT_LAYER) | - BITFIELD64_BIT(VARYING_SLOT_VIEWPORT); + zero_inputs &= VARYING_BIT_LAYER | + VARYING_BIT_VIEWPORT; if (zero_inputs) NIR_PASS(_, consumer, brw_nir_zero_inputs, &zero_inputs); diff --git a/src/intel/compiler/brw_nir_wa_18019110168.c b/src/intel/compiler/brw_nir_wa_18019110168.c index 66749a01b23..d1b5e03b2f2 100644 --- a/src/intel/compiler/brw_nir_wa_18019110168.c +++ b/src/intel/compiler/brw_nir_wa_18019110168.c @@ -99,19 +99,19 @@ mesh_convert_attrs_prim_to_vert(struct nir_shader *nir, const uint64_t outputs_written = nir->info.outputs_written; const uint64_t per_primitive_outputs = nir->info.per_primitive_outputs & - ~BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES); + ~VARYING_BIT_PRIMITIVE_INDICES; const uint64_t other_outputs = outputs_written & ~per_primitive_outputs; uint64_t all_outputs = outputs_written; const uint64_t remapped_outputs = outputs_written & nir->info.per_primitive_outputs & - ~(BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE) | - BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_INDICES) | - BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_COUNT) | - BITFIELD64_BIT(VARYING_SLOT_LAYER) | - BITFIELD64_BIT(VARYING_SLOT_VIEWPORT) | - BITFIELD64_BIT(VARYING_SLOT_PRIMITIVE_SHADING_RATE)); + ~(VARYING_BIT_CULL_PRIMITIVE | + VARYING_BIT_PRIMITIVE_INDICES | + VARYING_BIT_PRIMITIVE_COUNT | + VARYING_BIT_LAYER | + VARYING_BIT_VIEWPORT | + VARYING_BIT_PRIMITIVE_SHADING_RATE); /* indexed by slot of per-prim attribute */ struct mapping mapping[VARYING_SLOT_MAX] = { {NULL, NULL, NULL}, }; diff --git a/src/intel/compiler/elk/elk_fs.cpp b/src/intel/compiler/elk/elk_fs.cpp index 139f703cbc1..1ef4342e066 100644 --- a/src/intel/compiler/elk/elk_fs.cpp +++ b/src/intel/compiler/elk/elk_fs.cpp @@ -1470,7 +1470,7 @@ calculate_urb_setup(const struct intel_device_info *devinfo, * * See compile_sf_prog() for more info. */ - if (inputs_read & BITFIELD64_BIT(VARYING_SLOT_PNTC)) + if (inputs_read & VARYING_BIT_PNTC) prog_data->urb_setup[VARYING_SLOT_PNTC] = urb_next++; } diff --git a/src/intel/compiler/elk/elk_vue_map.c b/src/intel/compiler/elk/elk_vue_map.c index e119b2e31db..2d0a9e7da8e 100644 --- a/src/intel/compiler/elk/elk_vue_map.c +++ b/src/intel/compiler/elk/elk_vue_map.c @@ -82,8 +82,8 @@ elk_compute_vue_map(const struct intel_device_info *devinfo, * Note that we don't have to worry about COL/BFC, as those built-in * variables only exist in legacy GL, which only supports VS and FS. */ - slots_valid |= BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST0); - slots_valid |= BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST1); + slots_valid |= VARYING_BIT_CLIP_DIST0; + slots_valid |= VARYING_BIT_CLIP_DIST1; } vue_map->slots_valid = slots_valid; @@ -149,9 +149,9 @@ elk_compute_vue_map(const struct intel_device_info *devinfo, } } - if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST0)) + if (slots_valid & VARYING_BIT_CLIP_DIST0) assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST0, slot++); - if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST1)) + if (slots_valid & VARYING_BIT_CLIP_DIST1) assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST1, slot++); /* Vertex URB Formats table says: "Vertex Header shall be padded at the @@ -163,13 +163,13 @@ elk_compute_vue_map(const struct intel_device_info *devinfo, * ATTRIBUTE_SWIZZLE_INPUTATTR_FACING to swizzle them when doing * two-sided color. */ - if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_COL0)) + if (slots_valid & VARYING_BIT_COL0) assign_vue_slot(vue_map, VARYING_SLOT_COL0, slot++); - if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_BFC0)) + if (slots_valid & VARYING_BIT_BFC0) assign_vue_slot(vue_map, VARYING_SLOT_BFC0, slot++); - if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_COL1)) + if (slots_valid & VARYING_BIT_COL1) assign_vue_slot(vue_map, VARYING_SLOT_COL1, slot++); - if (slots_valid & BITFIELD64_BIT(VARYING_SLOT_BFC1)) + if (slots_valid & VARYING_BIT_BFC1) assign_vue_slot(vue_map, VARYING_SLOT_BFC1, slot++); } diff --git a/src/mesa/state_tracker/st_util.h b/src/mesa/state_tracker/st_util.h index 73179e7da64..5d710e30b5f 100644 --- a/src/mesa/state_tracker/st_util.h +++ b/src/mesa/state_tracker/st_util.h @@ -80,7 +80,7 @@ st_point_size_per_vertex(struct gl_context *ctx) if (vertProg) { if (vertProg->Id == 0) { if (vertProg->info.outputs_written & - BITFIELD64_BIT(VARYING_SLOT_PSIZ)) { + VARYING_BIT_PSIZ) { /* generated program which emits point size */ return true; } @@ -101,7 +101,7 @@ st_point_size_per_vertex(struct gl_context *ctx) last = ctx->VertexProgram._Current; if (last) return !!(last->info.outputs_written & - BITFIELD64_BIT(VARYING_SLOT_PSIZ)); + VARYING_BIT_PSIZ); } } return false; diff --git a/src/panfrost/compiler/bifrost_compile.c b/src/panfrost/compiler/bifrost_compile.c index d892632e069..db246c24906 100644 --- a/src/panfrost/compiler/bifrost_compile.c +++ b/src/panfrost/compiler/bifrost_compile.c @@ -5885,7 +5885,7 @@ bifrost_preprocess_nir(nir_shader *nir, unsigned gpu_id) } else if (nir->info.stage == MESA_SHADER_VERTEX) { if (gpu_id >= 0x9000) { NIR_PASS(_, nir, nir_lower_mediump_io, nir_var_shader_out, - BITFIELD64_BIT(VARYING_SLOT_PSIZ), false); + VARYING_BIT_PSIZ, false); } NIR_PASS(_, nir, pan_nir_lower_store_component); @@ -6328,15 +6328,13 @@ bi_compile_variant(nir_shader *nir, * written (that mean not position, layer or point size) */ info->vs.secondary_enable = (nir->info.outputs_written & - ~(BITFIELD64_BIT(VARYING_SLOT_POS) | - BITFIELD64_BIT(VARYING_SLOT_LAYER) | - BITFIELD64_BIT(VARYING_SLOT_PSIZ))) != 0; + ~(VARYING_BIT_POS | VARYING_BIT_LAYER | VARYING_BIT_PSIZ)) != 0; } } if ((idvs == BI_IDVS_POSITION || idvs == BI_IDVS_ALL) && !nir->info.internal && - nir->info.outputs_written & BITFIELD_BIT(VARYING_SLOT_PSIZ)) { + nir->info.outputs_written & VARYING_BIT_PSIZ) { /* Find the psiz write */ bi_instr *write = NULL; @@ -6379,7 +6377,7 @@ bi_should_idvs(nir_shader *nir, const struct pan_compile_inputs *inputs) /* Bifrost cannot write gl_PointSize during IDVS */ if ((inputs->gpu_id < 0x9000) && - nir->info.outputs_written & BITFIELD_BIT(VARYING_SLOT_PSIZ)) + nir->info.outputs_written & VARYING_BIT_PSIZ) return false; /* Otherwise, IDVS is usually better */ diff --git a/src/panfrost/lib/pan_shader.c b/src/panfrost/lib/pan_shader.c index c179df6dc57..e34df547528 100644 --- a/src/panfrost/lib/pan_shader.c +++ b/src/panfrost/lib/pan_shader.c @@ -92,7 +92,7 @@ pan_shader_compile(nir_shader *s, struct pan_compile_inputs *inputs, } info->vs.writes_point_size = - s->info.outputs_written & (1 << VARYING_SLOT_PSIZ); + s->info.outputs_written & VARYING_BIT_PSIZ; if (arch >= 9) { info->varyings.output_count = @@ -141,15 +141,15 @@ pan_shader_compile(nir_shader *s, struct pan_compile_inputs *inputs, info->contains_barrier |= s->info.fs.needs_coarse_quad_helper_invocations; info->fs.reads_frag_coord = - (s->info.inputs_read & (1 << VARYING_SLOT_POS)) || + (s->info.inputs_read & VARYING_BIT_POS) || BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_FRAG_COORD); info->fs.reads_primitive_id = - (s->info.inputs_read & (1 << VARYING_SLOT_PRIMITIVE_ID)) || + (s->info.inputs_read & VARYING_BIT_PRIMITIVE_ID) || BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID); info->fs.reads_point_coord = - s->info.inputs_read & (1 << VARYING_SLOT_PNTC); + s->info.inputs_read & VARYING_BIT_PNTC; info->fs.reads_face = - (s->info.inputs_read & (1 << VARYING_SLOT_FACE)) || + (s->info.inputs_read & VARYING_BIT_FACE) || BITSET_TEST(s->info.system_values_read, SYSTEM_VALUE_FRONT_FACE); if (arch >= 9) { info->varyings.input_count =