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synced 2025-12-27 01:50:10 +01:00
ilo: use ilo_builder for kernels and STATE_BASE_ADDRESS
Remove instruction buffer management from ilo_3d and adapt ilo_shader_cache to upload kernels to ilo_builder. To be able to do that, we also let ilo_builder manage STATE_BASE_ADDRESS.
This commit is contained in:
parent
55f80a3290
commit
d2acd67313
9 changed files with 61 additions and 201 deletions
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@ -401,7 +401,8 @@ ilo_3d_cp_flushed(struct ilo_3d *hw3d)
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/* invalidate the pipeline */
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ilo_3d_pipeline_invalidate(hw3d->pipeline,
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ILO_3D_PIPELINE_INVALIDATE_BATCH_BO |
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ILO_3D_PIPELINE_INVALIDATE_STATE_BO);
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ILO_3D_PIPELINE_INVALIDATE_STATE_BO |
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ILO_3D_PIPELINE_INVALIDATE_KERNEL_BO);
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hw3d->new_batch = true;
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}
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@ -446,10 +447,6 @@ void
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ilo_3d_destroy(struct ilo_3d *hw3d)
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{
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ilo_3d_pipeline_destroy(hw3d->pipeline);
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if (hw3d->kernel.bo)
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intel_bo_unreference(hw3d->kernel.bo);
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FREE(hw3d);
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}
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@ -717,66 +714,6 @@ ilo_draw_vbo_with_sw_restart(struct pipe_context *pipe,
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FREE(restart_info);
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}
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static bool
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upload_shaders(struct ilo_3d *hw3d, struct ilo_shader_cache *shc)
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{
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bool incremental = true;
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int upload;
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upload = ilo_shader_cache_upload(shc,
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NULL, hw3d->kernel.used, incremental);
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if (!upload)
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return true;
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/*
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* Allocate a new bo. When this is a new batch, assume the bo is still in
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* use by the previous batch and force allocation.
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*
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* Does it help to make shader cache upload with unsynchronized mapping,
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* and remove the check for new batch here?
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*/
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if (hw3d->kernel.used + upload > hw3d->kernel.size || hw3d->new_batch) {
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unsigned new_size = (hw3d->kernel.size) ?
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hw3d->kernel.size : (8 * 1024);
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while (hw3d->kernel.used + upload > new_size)
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new_size *= 2;
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if (hw3d->kernel.bo)
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intel_bo_unreference(hw3d->kernel.bo);
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hw3d->kernel.bo = intel_winsys_alloc_buffer(hw3d->cp->winsys,
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"kernel bo", new_size, true);
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if (!hw3d->kernel.bo) {
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ilo_err("failed to allocate kernel bo\n");
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return false;
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}
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hw3d->kernel.used = 0;
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hw3d->kernel.size = new_size;
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incremental = false;
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assert(new_size >= ilo_shader_cache_upload(shc,
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NULL, hw3d->kernel.used, incremental));
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ilo_3d_pipeline_invalidate(hw3d->pipeline,
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ILO_3D_PIPELINE_INVALIDATE_KERNEL_BO);
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}
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upload = ilo_shader_cache_upload(shc,
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hw3d->kernel.bo, hw3d->kernel.used, incremental);
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if (upload < 0) {
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ilo_err("failed to upload shaders\n");
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return false;
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}
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hw3d->kernel.used += upload;
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assert(hw3d->kernel.used <= hw3d->kernel.size);
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return true;
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}
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static void
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ilo_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
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{
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@ -816,8 +753,7 @@ ilo_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
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ilo_finalize_3d_states(ilo, info);
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if (!upload_shaders(hw3d, ilo->shader_cache))
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return;
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ilo_shader_cache_upload(ilo->shader_cache, &hw3d->cp->builder);
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ilo_blit_resolve_framebuffer(ilo);
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@ -45,11 +45,6 @@ struct ilo_3d {
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bool new_batch;
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struct {
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struct intel_bo *bo;
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unsigned used, size;
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} kernel;
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struct {
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struct pipe_query *query;
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unsigned mode;
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@ -215,15 +215,11 @@ gen6_pipeline_common_base_address(struct ilo_3d_pipeline *p,
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/* STATE_BASE_ADDRESS */
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if (session->state_bo_changed || session->kernel_bo_changed ||
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session->batch_bo_changed) {
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const struct ilo_builder_writer *bat =
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&p->cp->builder.writers[ILO_BUILDER_WRITER_BATCH];
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if (p->dev->gen == ILO_GEN(6))
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gen6_wa_pipe_control_post_sync(p, false);
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gen6_emit_STATE_BASE_ADDRESS(p->dev,
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NULL, bat->bo, bat->bo, NULL, ilo->hw3d->kernel.bo,
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0, 0, 0, 0, p->cp);
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ilo_builder_batch_state_base_address(&p->cp->builder,
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session->hw_ctx_changed);
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/*
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* From the Sandy Bridge PRM, volume 1 part 1, page 28:
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@ -1634,13 +1630,7 @@ gen6_rectlist_commands(struct ilo_3d_pipeline *p,
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gen6_rectlist_wm_multisample(p, blitter, session);
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gen6_emit_STATE_BASE_ADDRESS(p->dev,
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NULL, /* General State Base */
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p->cp->builder.writers[0].bo, /* Surface State Base */
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p->cp->builder.writers[0].bo, /* Dynamic State Base */
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NULL, /* Indirect Object Base */
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NULL, /* Instruction Base */
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0, 0, 0, 0, p->cp);
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ilo_builder_batch_state_base_address(&p->cp->builder, true);
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gen6_emit_3DSTATE_VERTEX_BUFFERS(p->dev,
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&blitter->ve, &blitter->vb, p->cp);
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@ -800,13 +800,7 @@ gen7_rectlist_commands(struct ilo_3d_pipeline *p,
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{
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gen7_rectlist_wm_multisample(p, blitter, session);
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gen6_emit_STATE_BASE_ADDRESS(p->dev,
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NULL, /* General State Base */
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p->cp->builder.writers[0].bo, /* Surface State Base */
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p->cp->builder.writers[0].bo, /* Dynamic State Base */
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NULL, /* Indirect Object Base */
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NULL, /* Instruction Base */
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0, 0, 0, 0, p->cp);
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ilo_builder_batch_state_base_address(&p->cp->builder, true);
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gen6_emit_3DSTATE_VERTEX_BUFFERS(p->dev,
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&blitter->ve, &blitter->vb, p->cp);
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@ -109,8 +109,8 @@ ilo_context_create(struct pipe_screen *screen, void *priv)
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util_slab_create(&ilo->transfer_mempool,
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sizeof(struct ilo_transfer), 64, UTIL_SLAB_SINGLETHREADED);
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ilo->cp = ilo_cp_create(ilo->dev, ilo->winsys);
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ilo->shader_cache = ilo_shader_cache_create();
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ilo->cp = ilo_cp_create(ilo->dev, ilo->winsys, ilo->shader_cache);
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if (ilo->cp)
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ilo->hw3d = ilo_3d_create(ilo->cp, ilo->dev);
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@ -27,11 +27,14 @@
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#include "intel_winsys.h"
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#include "ilo_shader.h"
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#include "ilo_cp.h"
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static struct intel_bo *
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ilo_cp_end_batch(struct ilo_cp *cp, unsigned *used)
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{
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struct intel_bo *bo;
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ilo_cp_set_owner(cp, NULL, 0);
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if (!ilo_builder_batch_used(&cp->builder)) {
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@ -43,7 +46,13 @@ ilo_cp_end_batch(struct ilo_cp *cp, unsigned *used)
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assert(ilo_builder_batch_space(&cp->builder) >= 2);
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ilo_builder_batch_mi_batch_buffer_end(&cp->builder);
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return ilo_builder_end(&cp->builder, used);
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bo = ilo_builder_end(&cp->builder, used);
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/* we have to assume that kernel uploads also failed */
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if (!bo)
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ilo_shader_cache_invalidate(cp->shader_cache);
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return bo;
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}
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/**
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@ -101,7 +110,9 @@ ilo_cp_destroy(struct ilo_cp *cp)
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* Create a command parser.
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*/
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struct ilo_cp *
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ilo_cp_create(const struct ilo_dev_info *dev, struct intel_winsys *winsys)
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ilo_cp_create(const struct ilo_dev_info *dev,
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struct intel_winsys *winsys,
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struct ilo_shader_cache *shc)
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{
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struct ilo_cp *cp;
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@ -110,6 +121,7 @@ ilo_cp_create(const struct ilo_dev_info *dev, struct intel_winsys *winsys)
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return NULL;
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cp->winsys = winsys;
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cp->shader_cache = shc;
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cp->render_ctx = intel_winsys_create_context(winsys);
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if (!cp->render_ctx) {
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FREE(cp);
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@ -34,6 +34,7 @@
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#include "ilo_common.h"
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struct ilo_cp;
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struct ilo_shader_cache;
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typedef void (*ilo_cp_callback)(struct ilo_cp *cp, void *data);
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@ -47,6 +48,7 @@ struct ilo_cp_owner {
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*/
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struct ilo_cp {
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struct intel_winsys *winsys;
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struct ilo_shader_cache *shader_cache;
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struct intel_context *render_ctx;
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ilo_cp_callback flush_callback;
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@ -68,7 +70,9 @@ struct ilo_cp {
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};
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struct ilo_cp *
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ilo_cp_create(const struct ilo_dev_info *dev, struct intel_winsys *winsys);
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ilo_cp_create(const struct ilo_dev_info *dev,
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struct intel_winsys *winsys,
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struct ilo_shader_cache *shc);
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void
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ilo_cp_destroy(struct ilo_cp *cp);
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@ -30,6 +30,7 @@
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#include "intel_winsys.h"
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#include "shader/ilo_shader_internal.h"
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#include "ilo_builder.h"
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#include "ilo_state.h"
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#include "ilo_shader.h"
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@ -107,128 +108,53 @@ ilo_shader_cache_notify_change(struct ilo_shader_cache *shc,
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}
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/**
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* Upload a managed shader to the bo.
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* Upload managed shaders to the bo. Only shaders that are changed or added
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* after the last upload are uploaded.
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*/
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static int
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ilo_shader_cache_upload_shader(struct ilo_shader_cache *shc,
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struct ilo_shader_state *shader,
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struct intel_bo *bo, unsigned offset,
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bool incremental)
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void
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ilo_shader_cache_upload(struct ilo_shader_cache *shc,
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struct ilo_builder *builder)
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{
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const unsigned base = offset;
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struct ilo_shader *sh;
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struct ilo_shader_state *shader, *next;
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LIST_FOR_EACH_ENTRY(sh, &shader->variants, list) {
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int err;
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LIST_FOR_EACH_ENTRY_SAFE(shader, next, &shc->changed, list) {
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struct ilo_shader *sh;
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if (incremental && sh->uploaded)
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continue;
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LIST_FOR_EACH_ENTRY(sh, &shader->variants, list) {
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if (sh->uploaded)
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continue;
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/* kernels must be aligned to 64-byte */
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offset = align(offset, 64);
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sh->cache_offset = ilo_builder_instruction_write(builder,
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sh->kernel_size, sh->kernel);
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err = intel_bo_pwrite(bo, offset, sh->kernel_size, sh->kernel);
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if (unlikely(err))
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return -1;
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sh->uploaded = true;
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}
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sh->uploaded = true;
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sh->cache_offset = offset;
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offset += sh->kernel_size;
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list_del(&shader->list);
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list_add(&shader->list, &shc->shaders);
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}
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return (int) (offset - base);
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}
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/**
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* Similar to ilo_shader_cache_upload(), except no upload happens.
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* Invalidate all shaders so that they get uploaded in next
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* ilo_shader_cache_upload().
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*/
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static int
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ilo_shader_cache_get_upload_size(struct ilo_shader_cache *shc,
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unsigned offset,
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bool incremental)
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void
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ilo_shader_cache_invalidate(struct ilo_shader_cache *shc)
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{
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const unsigned base = offset;
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struct ilo_shader_state *shader;
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struct ilo_shader_state *shader, *next;
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if (!incremental) {
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LIST_FOR_EACH_ENTRY(shader, &shc->shaders, list) {
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struct ilo_shader *sh;
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/* see ilo_shader_cache_upload_shader() */
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LIST_FOR_EACH_ENTRY(sh, &shader->variants, list) {
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if (!incremental || !sh->uploaded)
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offset = align(offset, 64) + sh->kernel_size;
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}
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}
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LIST_FOR_EACH_ENTRY_SAFE(shader, next, &shc->shaders, list) {
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list_del(&shader->list);
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list_add(&shader->list, &shc->changed);
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}
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LIST_FOR_EACH_ENTRY(shader, &shc->changed, list) {
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struct ilo_shader *sh;
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/* see ilo_shader_cache_upload_shader() */
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LIST_FOR_EACH_ENTRY(sh, &shader->variants, list) {
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if (!incremental || !sh->uploaded)
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offset = align(offset, 64) + sh->kernel_size;
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}
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LIST_FOR_EACH_ENTRY(sh, &shader->variants, list)
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sh->uploaded = false;
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}
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/*
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* From the Sandy Bridge PRM, volume 4 part 2, page 112:
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*
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* "Due to prefetch of the instruction stream, the EUs may attempt to
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* access up to 8 instructions (128 bytes) beyond the end of the
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* kernel program - possibly into the next memory page. Although
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* these instructions will not be executed, software must account for
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* the prefetch in order to avoid invalid page access faults."
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*/
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if (offset > base)
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offset += 128;
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return (int) (offset - base);
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}
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/**
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* Upload managed shaders to the bo. When incremental is true, only shaders
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* that are changed or added after the last upload are uploaded.
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*/
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int
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ilo_shader_cache_upload(struct ilo_shader_cache *shc,
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struct intel_bo *bo, unsigned offset,
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bool incremental)
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{
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struct ilo_shader_state *shader, *next;
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int size = 0, s;
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if (!bo)
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return ilo_shader_cache_get_upload_size(shc, offset, incremental);
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if (!incremental) {
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LIST_FOR_EACH_ENTRY(shader, &shc->shaders, list) {
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s = ilo_shader_cache_upload_shader(shc, shader,
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bo, offset, incremental);
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if (unlikely(s < 0))
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return s;
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size += s;
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offset += s;
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}
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}
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LIST_FOR_EACH_ENTRY_SAFE(shader, next, &shc->changed, list) {
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s = ilo_shader_cache_upload_shader(shc, shader,
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bo, offset, incremental);
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if (unlikely(s < 0))
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return s;
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size += s;
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offset += s;
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list_del(&shader->list);
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list_add(&shader->list, &shc->shaders);
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}
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return size;
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}
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/**
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@ -70,6 +70,7 @@ struct ilo_kernel_routing {
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};
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struct intel_bo;
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struct ilo_builder;
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struct ilo_context;
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struct ilo_rasterizer_state;
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struct ilo_shader_cache;
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@ -90,10 +91,12 @@ void
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ilo_shader_cache_remove(struct ilo_shader_cache *shc,
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struct ilo_shader_state *shader);
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int
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void
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ilo_shader_cache_upload(struct ilo_shader_cache *shc,
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struct intel_bo *bo, unsigned offset,
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bool incremental);
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struct ilo_builder *builder);
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void
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ilo_shader_cache_invalidate(struct ilo_shader_cache *shc);
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struct ilo_shader_state *
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ilo_shader_create_vs(const struct ilo_dev_info *dev,
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