diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
index 4f49428ef3f..a1a201b8b5f 100644
--- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h
@@ -254,6 +254,32 @@ set_saturate(bool saturate, vec4_instruction *inst)
    return inst;
 }
 
+/**
+ * Return the number of dataflow registers written by the instruction (either
+ * fully or partially) counted from 'floor(reg_offset(inst->dst) /
+ * register_size)'.  The somewhat arbitrary register size unit is 16B for the
+ * UNIFORM and IMM files and 32B for all other files.
+ */
+inline unsigned
+regs_written(const vec4_instruction *inst)
+{
+   /* XXX - Take into account register-misaligned offsets correctly. */
+   return inst->regs_written;
+}
+
+/**
+ * Return the number of dataflow registers read by the instruction (either
+ * fully or partially) counted from 'floor(reg_offset(inst->src[i]) /
+ * register_size)'.  The somewhat arbitrary register size unit is 16B for the
+ * UNIFORM and IMM files and 32B for all other files.
+ */
+inline unsigned
+regs_read(const vec4_instruction *inst, unsigned i)
+{
+   /* XXX - Take into account register-misaligned offsets correctly. */
+   return inst->regs_read(i);
+}
+
 } /* namespace brw */
 
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 0d3a07cad5b..c12bf09e835 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -1269,7 +1269,7 @@ vec4_instruction_scheduler::calculate_deps()
       /* read-after-write deps. */
       for (int i = 0; i < 3; i++) {
          if (inst->src[i].file == VGRF) {
-            for (unsigned j = 0; j < inst->regs_read(i); ++j)
+            for (unsigned j = 0; j < regs_read(inst, i); ++j)
                add_dep(last_grf_write[inst->src[i].nr + j], n);
          } else if (inst->src[i].file == FIXED_GRF) {
             add_dep(last_fixed_grf_write, n);
@@ -1303,7 +1303,7 @@ vec4_instruction_scheduler::calculate_deps()
 
       /* write-after-write deps. */
       if (inst->dst.file == VGRF) {
-         for (unsigned j = 0; j < inst->regs_written; ++j) {
+         for (unsigned j = 0; j < regs_written(inst); ++j) {
             add_dep(last_grf_write[inst->dst.nr + j], n);
             last_grf_write[inst->dst.nr + j] = n;
          }
@@ -1351,7 +1351,7 @@ vec4_instruction_scheduler::calculate_deps()
       /* write-after-read deps. */
       for (int i = 0; i < 3; i++) {
          if (inst->src[i].file == VGRF) {
-            for (unsigned j = 0; j < inst->regs_read(i); ++j)
+            for (unsigned j = 0; j < regs_read(inst, i); ++j)
                add_dep(n, last_grf_write[inst->src[i].nr + j]);
          } else if (inst->src[i].file == FIXED_GRF) {
             add_dep(n, last_fixed_grf_write);
@@ -1384,7 +1384,7 @@ vec4_instruction_scheduler::calculate_deps()
        * can mark this as WAR dependency.
        */
       if (inst->dst.file == VGRF) {
-         for (unsigned j = 0; j < inst->regs_written; ++j)
+         for (unsigned j = 0; j < regs_written(inst); ++j)
             last_grf_write[inst->dst.nr + j] = n;
       } else if (inst->dst.file == MRF) {
          last_mrf_write[inst->dst.nr] = n;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index de5b5d6c838..3e57addb7a4 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1335,11 +1335,11 @@ vec4_visitor::split_virtual_grfs()
     * to split.
     */
    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
-      if (inst->dst.file == VGRF && inst->regs_written > 1)
+      if (inst->dst.file == VGRF && regs_written(inst) > 1)
          split_grf[inst->dst.nr] = false;
 
       for (int i = 0; i < 3; i++) {
-         if (inst->src[i].file == VGRF && inst->regs_read(i) > 1)
+         if (inst->src[i].file == VGRF && regs_read(inst, i) > 1)
             split_grf[inst->src[i].nr] = false;
       }
    }
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
index 10898a5917d..f0908b93fc9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp
@@ -178,10 +178,10 @@ vec4_visitor::opt_cse_local(bblock_t *block)
             bool no_existing_temp = entry->tmp.file == BAD_FILE;
             if (no_existing_temp && !entry->generator->dst.is_null()) {
                entry->tmp = retype(src_reg(VGRF, alloc.allocate(
-                                              entry->generator->regs_written),
+                                              regs_written(entry->generator)),
                                            NULL), inst->dst.type);
 
-               for (unsigned i = 0; i < entry->generator->regs_written; ++i) {
+               for (unsigned i = 0; i < regs_written(entry->generator); ++i) {
                   vec4_instruction *copy = MOV(offset(entry->generator->dst, i),
                                                offset(entry->tmp, i));
                   copy->force_writemask_all =
@@ -196,7 +196,7 @@ vec4_visitor::opt_cse_local(bblock_t *block)
             if (!inst->dst.is_null()) {
                assert(inst->dst.type == entry->tmp.type);
 
-               for (unsigned i = 0; i < inst->regs_written; ++i) {
+               for (unsigned i = 0; i < regs_written(inst); ++i) {
                   vec4_instruction *copy = MOV(offset(inst->dst, i),
                                                offset(entry->tmp, i));
                   copy->force_writemask_all = inst->force_writemask_all;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
index c643212494b..50706a977cb 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_dead_code_eliminate.cpp
@@ -59,7 +59,7 @@ vec4_visitor::dead_code_eliminate()
             bool result_live[4] = { false };
 
             if (inst->dst.file == VGRF) {
-               for (unsigned i = 0; i < inst->regs_written; i++) {
+               for (unsigned i = 0; i < regs_written(inst); i++) {
                   for (int c = 0; c < 4; c++)
                      result_live[c] |= BITSET_TEST(
                         live, var_from_reg(alloc, offset(inst->dst, i), c));
@@ -110,7 +110,7 @@ vec4_visitor::dead_code_eliminate()
          }
 
          if (inst->dst.file == VGRF && !inst->predicate) {
-            for (unsigned i = 0; i < inst->regs_written; i++) {
+            for (unsigned i = 0; i < regs_written(inst); i++) {
                for (int c = 0; c < 4; c++) {
                   if (inst->dst.writemask & (1 << c)) {
                      BITSET_CLEAR(live, var_from_reg(alloc,
@@ -132,7 +132,7 @@ vec4_visitor::dead_code_eliminate()
 
          for (int i = 0; i < 3; i++) {
             if (inst->src[i].file == VGRF) {
-               for (unsigned j = 0; j < inst->regs_read(i); j++) {
+               for (unsigned j = 0; j < regs_read(inst, i); j++) {
                   for (int c = 0; c < 4; c++) {
                      BITSET_SET(live, var_from_reg(alloc,
                                                    offset(inst->src[i], j), c));
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp
index 57d5fbb75dd..20344ed1770 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.cpp
@@ -76,7 +76,7 @@ vec4_live_variables::setup_def_use()
 	 /* Set use[] for this instruction */
 	 for (unsigned int i = 0; i < 3; i++) {
 	    if (inst->src[i].file == VGRF) {
-               for (unsigned j = 0; j < inst->regs_read(i); j++) {
+               for (unsigned j = 0; j < regs_read(inst, i); j++) {
                   for (int c = 0; c < 4; c++) {
                      const unsigned v =
                         var_from_reg(alloc, offset(inst->src[i], j), c);
@@ -99,7 +99,7 @@ vec4_live_variables::setup_def_use()
 	  */
 	 if (inst->dst.file == VGRF &&
 	     (!inst->predicate || inst->opcode == BRW_OPCODE_SEL)) {
-            for (unsigned i = 0; i < inst->regs_written; i++) {
+            for (unsigned i = 0; i < regs_written(inst); i++) {
                for (int c = 0; c < 4; c++) {
                   if (inst->dst.writemask & (1 << c)) {
                      const unsigned v =
@@ -257,7 +257,7 @@ vec4_visitor::calculate_live_intervals()
    foreach_block_and_inst(block, vec4_instruction, inst, cfg) {
       for (unsigned int i = 0; i < 3; i++) {
 	 if (inst->src[i].file == VGRF) {
-            for (unsigned j = 0; j < inst->regs_read(i); j++) {
+            for (unsigned j = 0; j < regs_read(inst, i); j++) {
                for (int c = 0; c < 4; c++) {
                   const unsigned v =
                      var_from_reg(alloc, offset(inst->src[i], j), c);
@@ -269,7 +269,7 @@ vec4_visitor::calculate_live_intervals()
       }
 
       if (inst->dst.file == VGRF) {
-         for (unsigned i = 0; i < inst->regs_written; i++) {
+         for (unsigned i = 0; i < regs_written(inst); i++) {
             for (int c = 0; c < 4; c++) {
                if (inst->dst.writemask & (1 << c)) {
                   const unsigned v =