diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index 006dd1469a0..24aa7f0928d 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c @@ -260,6 +260,16 @@ blorp_get_l3_config(struct blorp_batch *batch) return cmd_buffer->state.current_l3_config; } +static bool +blorp_uses_bti_rt_writes(const struct blorp_batch *batch, const struct blorp_params *params) +{ + if (batch->flags & (BLORP_BATCH_USE_BLITTER | BLORP_BATCH_USE_COMPUTE)) + return false; + + /* HIZ clears use WM_HZ ops rather than a clear shader using RT writes. */ + return params->hiz_op == ISL_AUX_OP_NONE; +} + static void blorp_exec_on_render(struct blorp_batch *batch, const struct blorp_params *params) @@ -282,10 +292,12 @@ blorp_exec_on_render(struct blorp_batch *batch, * is set due to new association of BTI, PS Scoreboard Stall bit must * be set in this packet." */ - anv_add_pending_pipe_bits(cmd_buffer, - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | - ANV_PIPE_STALL_AT_SCOREBOARD_BIT, - "before blorp BTI change"); + if (blorp_uses_bti_rt_writes(batch, params)) { + anv_add_pending_pipe_bits(cmd_buffer, + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | + ANV_PIPE_STALL_AT_SCOREBOARD_BIT, + "before blorp BTI change"); + } #endif if (params->depth.enabled && @@ -316,10 +328,12 @@ blorp_exec_on_render(struct blorp_batch *batch, * is set due to new association of BTI, PS Scoreboard Stall bit must * be set in this packet." */ - anv_add_pending_pipe_bits(cmd_buffer, - ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | - ANV_PIPE_STALL_AT_SCOREBOARD_BIT, - "after blorp BTI change"); + if (blorp_uses_bti_rt_writes(batch, params)) { + anv_add_pending_pipe_bits(cmd_buffer, + ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | + ANV_PIPE_STALL_AT_SCOREBOARD_BIT, + "after blorp BTI change"); + } #endif /* Calculate state that does not get touched by blorp.