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r600g: texture buffer object + glsl 1.40 enable support (v2)
This adds TBO support to r600g, and with GLSL 1.40 enabled, we now get 3.1 core profiles advertised for r600g. The r600/700 implementation is a bit different from the evergreen one, as r6/7 hw lacks vertex fetch swizzles. So we implement it by passing 5 constants per sampler to the shader, the shader uses the first 4 as masks for each component and the 5th as the alpha value to OR in. Now TXQ is also broken so we have to pass a constant for the buffer size, on evergreen we just pass this, on r6/7 we pass it as the 6th element in the const info buffer. v1.1: drop return as DDX doesn't use a texture type v2: add r600/700 support. Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
parent
77c10225ee
commit
d23aa65001
10 changed files with 373 additions and 19 deletions
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@ -969,6 +969,58 @@ static void *evergreen_create_sampler_state(struct pipe_context *ctx,
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return ss;
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}
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static struct pipe_sampler_view *
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texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
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unsigned width0, unsigned height0)
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{
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struct pipe_context *ctx = view->base.context;
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struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
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uint64_t va;
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int stride = util_format_get_blocksize(view->base.format);
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unsigned format, num_format, format_comp, endian;
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unsigned swizzle_res;
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unsigned char swizzle[4];
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const struct util_format_description *desc;
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swizzle[0] = view->base.swizzle_r;
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swizzle[1] = view->base.swizzle_g;
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swizzle[2] = view->base.swizzle_b;
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swizzle[3] = view->base.swizzle_a;
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r600_vertex_data_type(view->base.format,
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&format, &num_format, &format_comp,
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&endian);
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desc = util_format_description(view->base.format);
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swizzle_res = r600_get_swizzle_combined(desc->swizzle, swizzle, TRUE);
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va = r600_resource_va(ctx->screen, view->base.texture);
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view->tex_resource = &tmp->resource;
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view->skip_mip_address_reloc = true;
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view->tex_resource_words[0] = va;
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view->tex_resource_words[1] = width0 - 1;
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view->tex_resource_words[2] = S_030008_BASE_ADDRESS_HI(va >> 32UL) |
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S_030008_STRIDE(stride) |
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S_030008_DATA_FORMAT(format) |
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S_030008_NUM_FORMAT_ALL(num_format) |
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S_030008_FORMAT_COMP_ALL(format_comp) |
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S_030008_SRF_MODE_ALL(1) |
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S_030008_ENDIAN_SWAP(endian);
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view->tex_resource_words[3] = swizzle_res;
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/*
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* in theory dword 4 is for number of elements, for use with resinfo,
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* but it seems to utterly fail to work, the amd gpu shader analyser
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* uses a const buffer to store the element sizes for buffer txq
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*/
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view->tex_resource_words[4] = 0;
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view->tex_resource_words[5] = view->tex_resource_words[6] = 0;
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view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER);
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return &view->base;
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}
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struct pipe_sampler_view *
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evergreen_create_sampler_view_custom(struct pipe_context *ctx,
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struct pipe_resource *texture,
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@ -997,6 +1049,9 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx,
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view->base.reference.count = 1;
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view->base.context = ctx;
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if (texture->target == PIPE_BUFFER)
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return texture_buffer_sampler_view(view, width0, height0);
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swizzle[0] = state->swizzle_r;
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swizzle[1] = state->swizzle_g;
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swizzle[2] = state->swizzle_b;
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@ -2609,7 +2609,7 @@ void r600_bytecode_dump(struct r600_bytecode *bc)
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fprintf(stderr, "--------------------------------------\n");
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}
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static void r600_vertex_data_type(enum pipe_format pformat,
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void r600_vertex_data_type(enum pipe_format pformat,
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unsigned *format,
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unsigned *num_format, unsigned *format_comp, unsigned *endian)
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{
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@ -250,4 +250,6 @@ void r700_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint3
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void r600_bytecode_export_read(struct r600_bytecode_output *output, uint32_t word0, uint32_t word1);
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void eg_bytecode_export_read(struct r600_bytecode_output *output, uint32_t word0, uint32_t word1);
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void r600_vertex_data_type(enum pipe_format pformat, unsigned *format,
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unsigned *num_format, unsigned *format_comp, unsigned *endian);
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#endif
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@ -416,6 +416,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_COMPUTE:
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case PIPE_CAP_START_INSTANCE:
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case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
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case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
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return 1;
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case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
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@ -425,7 +426,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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return 256;
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case PIPE_CAP_GLSL_FEATURE_LEVEL:
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return 130;
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return 140;
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case PIPE_CAP_TEXTURE_MULTISAMPLE:
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return rscreen->msaa_texture_support != MSAA_TEXTURE_SAMPLE_ZERO;
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@ -450,7 +451,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
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case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
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case PIPE_CAP_VERTEX_COLOR_CLAMPED:
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case PIPE_CAP_USER_VERTEX_BUFFERS:
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case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
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return 0;
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/* Stream output. */
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@ -40,12 +40,13 @@
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#define R600_TRACE_CS 0
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#define R600_MAX_USER_CONST_BUFFERS 13
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#define R600_MAX_DRIVER_CONST_BUFFERS 2
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#define R600_MAX_DRIVER_CONST_BUFFERS 3
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#define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
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/* start driver buffers after user buffers */
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#define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
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#define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1)
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#define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2)
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#define R600_MAX_CONST_BUFFER_SIZE 4096
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@ -330,6 +331,7 @@ struct r600_samplerview_state {
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uint32_t compressed_depthtex_mask; /* which textures are depth */
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uint32_t compressed_colortex_mask;
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boolean dirty_txq_constants;
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boolean dirty_buffer_constants;
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};
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struct r600_sampler_states {
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@ -347,6 +349,8 @@ struct r600_textures_info {
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/* cube array txq workaround */
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uint32_t *txq_constants;
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/* buffer related workarounds */
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uint32_t *buffer_constants;
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};
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struct r600_fence {
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@ -678,6 +682,10 @@ struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
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const struct pipe_surface *templ,
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unsigned width, unsigned height);
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unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
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const unsigned char *swizzle_view,
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boolean vtx);
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/* r600_state_common.c */
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void r600_init_common_state_functions(struct r600_context *rctx);
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void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom);
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@ -3896,6 +3896,128 @@ static inline unsigned tgsi_tex_get_src_gpr(struct r600_shader_ctx *ctx,
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return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
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}
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static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx, boolean src_requires_loading)
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{
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struct r600_bytecode_vtx vtx;
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struct r600_bytecode_alu alu;
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
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int src_gpr, r, i;
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int id = tgsi_tex_get_src_gpr(ctx, 1);
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src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
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if (src_requires_loading) {
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for (i = 0; i < 4; i++) {
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
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r600_bytecode_src(&alu.src[0], &ctx->src[0], i);
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alu.dst.sel = ctx->temp_reg;
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alu.dst.chan = i;
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if (i == 3)
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alu.last = 1;
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alu.dst.write = 1;
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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}
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src_gpr = ctx->temp_reg;
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}
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memset(&vtx, 0, sizeof(vtx));
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vtx.inst = 0;
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vtx.buffer_id = id + R600_MAX_CONST_BUFFERS;
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vtx.fetch_type = 2; /* VTX_FETCH_NO_INDEX_OFFSET */
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vtx.src_gpr = src_gpr;
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vtx.mega_fetch_count = 16;
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vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
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vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
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vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
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vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
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vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
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vtx.use_const_fields = 1;
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vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
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if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
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return r;
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if (ctx->bc->chip_class >= EVERGREEN)
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return 0;
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for (i = 0; i < 4; i++) {
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int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
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if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
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continue;
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_AND_INT);
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alu.dst.chan = i;
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alu.dst.sel = vtx.dst_gpr;
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alu.dst.write = 1;
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alu.src[0].sel = vtx.dst_gpr;
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alu.src[0].chan = i;
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alu.src[1].sel = 512 + (id * 2);
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alu.src[1].chan = i % 4;
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alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
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if (i == lasti)
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alu.last = 1;
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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}
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if (inst->Dst[0].Register.WriteMask & 3) {
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_OR_INT);
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alu.dst.chan = 3;
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alu.dst.sel = vtx.dst_gpr;
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alu.dst.write = 1;
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alu.src[0].sel = vtx.dst_gpr;
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alu.src[0].chan = 3;
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alu.src[1].sel = 512 + (id * 2) + 1;
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alu.src[1].chan = 0;
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alu.src[1].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
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alu.last = 1;
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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}
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return 0;
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}
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static int r600_do_buffer_txq(struct r600_shader_ctx *ctx)
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{
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struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
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struct r600_bytecode_alu alu;
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int r;
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int id = tgsi_tex_get_src_gpr(ctx, 1);
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memset(&alu, 0, sizeof(struct r600_bytecode_alu));
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alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
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if (ctx->bc->chip_class >= EVERGREEN) {
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alu.src[0].sel = 512 + (id / 4);
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alu.src[0].chan = id % 4;
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} else {
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/* r600 we have them at channel 2 of the second dword */
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alu.src[0].sel = 512 + (id * 2) + 1;
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alu.src[0].chan = 1;
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}
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alu.src[0].kc_bank = R600_BUFFER_INFO_CONST_BUFFER;
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tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
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alu.last = 1;
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r = r600_bytecode_add_alu(ctx->bc, &alu);
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if (r)
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return r;
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return 0;
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}
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static int tgsi_tex(struct r600_shader_ctx *ctx)
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{
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static float one_point_five = 1.5f;
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@ -3934,6 +4056,18 @@ static int tgsi_tex(struct r600_shader_ctx *ctx)
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src_gpr = tgsi_tex_get_src_gpr(ctx, 0);
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if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
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if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
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ctx->shader->uses_tex_buffers = true;
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return r600_do_buffer_txq(ctx);
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}
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else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
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if (ctx->bc->chip_class < EVERGREEN)
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ctx->shader->uses_tex_buffers = true;
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return do_vtx_fetch_inst(ctx, src_requires_loading);
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}
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}
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if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
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/* get offset values */
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if (inst->Texture.NumOffsets) {
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@ -61,6 +61,7 @@ struct r600_shader {
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boolean vs_out_misc_write;
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boolean vs_out_point_size;
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boolean has_txq_cube_array_z_comp;
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boolean uses_tex_buffers;
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};
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struct r600_shader_key {
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@ -976,6 +976,46 @@ static void *r600_create_sampler_state(struct pipe_context *ctx,
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return ss;
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}
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static struct pipe_sampler_view *
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texture_buffer_sampler_view(struct r600_pipe_sampler_view *view,
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unsigned width0, unsigned height0)
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{
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struct pipe_context *ctx = view->base.context;
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struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
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uint64_t va;
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int stride = util_format_get_blocksize(view->base.format);
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unsigned format, num_format, format_comp, endian;
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r600_vertex_data_type(view->base.format,
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&format, &num_format, &format_comp,
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&endian);
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va = r600_resource_va(ctx->screen, view->base.texture);
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view->tex_resource = &tmp->resource;
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view->skip_mip_address_reloc = true;
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view->tex_resource_words[0] = va;
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view->tex_resource_words[1] = width0 - 1;
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view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(va >> 32UL) |
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S_038008_STRIDE(stride) |
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S_038008_DATA_FORMAT(format) |
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S_038008_NUM_FORMAT_ALL(num_format) |
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S_038008_FORMAT_COMP_ALL(format_comp) |
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S_038008_SRF_MODE_ALL(1) |
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S_038008_ENDIAN_SWAP(endian);
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view->tex_resource_words[3] = 0;
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/*
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* in theory dword 4 is for number of elements, for use with resinfo,
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* but it seems to utterly fail to work, the amd gpu shader analyser
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* uses a const buffer to store the element sizes for buffer txq
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*/
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view->tex_resource_words[4] = 0;
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view->tex_resource_words[5] = 0;
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view->tex_resource_words[6] = S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_BUFFER);
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return &view->base;
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}
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struct pipe_sampler_view *
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r600_create_sampler_view_custom(struct pipe_context *ctx,
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struct pipe_resource *texture,
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@ -1000,6 +1040,9 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
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view->base.reference.count = 1;
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view->base.context = ctx;
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if (texture->target == PIPE_BUFFER)
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return texture_buffer_sampler_view(view, texture->width0, 1);
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swizzle[0] = state->swizzle_r;
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swizzle[1] = state->swizzle_g;
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swizzle[2] = state->swizzle_b;
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@ -588,19 +588,20 @@ static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
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struct r600_texture *rtex =
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(struct r600_texture*)rviews[i]->base.texture;
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if (rtex->is_depth && !rtex->is_flushing_texture) {
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dst->views.compressed_depthtex_mask |= 1 << i;
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} else {
|
||||
dst->views.compressed_depthtex_mask &= ~(1 << i);
|
||||
}
|
||||
if (rviews[i]->base.texture->target != PIPE_BUFFER) {
|
||||
if (rtex->is_depth && !rtex->is_flushing_texture) {
|
||||
dst->views.compressed_depthtex_mask |= 1 << i;
|
||||
} else {
|
||||
dst->views.compressed_depthtex_mask &= ~(1 << i);
|
||||
}
|
||||
|
||||
/* Track compressed colorbuffers. */
|
||||
if (rtex->cmask_size && rtex->fmask_size) {
|
||||
dst->views.compressed_colortex_mask |= 1 << i;
|
||||
} else {
|
||||
dst->views.compressed_colortex_mask &= ~(1 << i);
|
||||
/* Track compressed colorbuffers. */
|
||||
if (rtex->cmask_size && rtex->fmask_size) {
|
||||
dst->views.compressed_colortex_mask |= 1 << i;
|
||||
} else {
|
||||
dst->views.compressed_colortex_mask &= ~(1 << i);
|
||||
}
|
||||
}
|
||||
|
||||
/* Changing from array to non-arrays textures and vice versa requires
|
||||
* updating TEX_ARRAY_OVERRIDE in sampler states on R6xx-R7xx. */
|
||||
if (rctx->chip_class <= R700 &&
|
||||
|
|
@ -625,6 +626,7 @@ static void r600_set_sampler_views(struct pipe_context *pipe, unsigned shader,
|
|||
dst->views.compressed_depthtex_mask &= dst->views.enabled_mask;
|
||||
dst->views.compressed_colortex_mask &= dst->views.enabled_mask;
|
||||
dst->views.dirty_txq_constants = TRUE;
|
||||
dst->views.dirty_buffer_constants = TRUE;
|
||||
r600_sampler_views_dirty(rctx, &dst->views);
|
||||
|
||||
if (dirty_sampler_states_mask) {
|
||||
|
|
@ -1023,6 +1025,92 @@ static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask
|
|||
rctx->sample_mask.atom.dirty = true;
|
||||
}
|
||||
|
||||
/*
|
||||
* On r600/700 hw we don't have vertex fetch swizzle, though TBO
|
||||
* doesn't require full swizzles it does need masking and setting alpha
|
||||
* to one, so we setup a set of 5 constants with the masks + alpha value
|
||||
* then in the shader, we AND the 4 components with 0xffffffff or 0,
|
||||
* then OR the alpha with the value given here.
|
||||
* We use a 6th constant to store the txq buffer size in
|
||||
*/
|
||||
static void r600_setup_buffer_constants(struct r600_context *rctx, int shader_type)
|
||||
{
|
||||
struct r600_textures_info *samplers = &rctx->samplers[shader_type];
|
||||
int bits;
|
||||
uint32_t array_size;
|
||||
struct pipe_constant_buffer cb;
|
||||
int i, j;
|
||||
|
||||
if (!samplers->views.dirty_buffer_constants)
|
||||
return;
|
||||
|
||||
samplers->views.dirty_buffer_constants = FALSE;
|
||||
|
||||
bits = util_last_bit(samplers->views.enabled_mask);
|
||||
array_size = bits * 8 * sizeof(uint32_t) * 4;
|
||||
samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
|
||||
memset(samplers->buffer_constants, 0, array_size);
|
||||
for (i = 0; i < bits; i++) {
|
||||
if (samplers->views.enabled_mask & (1 << i)) {
|
||||
int offset = i * 8;
|
||||
const struct util_format_description *desc;
|
||||
desc = util_format_description(samplers->views.views[i]->base.format);
|
||||
|
||||
for (j = 0; j < 4; j++)
|
||||
if (j < desc->nr_channels)
|
||||
samplers->buffer_constants[offset+j] = 0xffffffff;
|
||||
else
|
||||
samplers->buffer_constants[offset+j] = 0x0;
|
||||
if (desc->nr_channels < 4) {
|
||||
if (desc->channel[0].pure_integer)
|
||||
samplers->buffer_constants[offset+4] = 1;
|
||||
else
|
||||
samplers->buffer_constants[offset+4] = 0x3f800000;
|
||||
} else
|
||||
samplers->buffer_constants[offset + 4] = 0;
|
||||
|
||||
samplers->buffer_constants[offset + 5] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
|
||||
}
|
||||
}
|
||||
|
||||
cb.buffer = NULL;
|
||||
cb.user_buffer = samplers->buffer_constants;
|
||||
cb.buffer_offset = 0;
|
||||
cb.buffer_size = array_size;
|
||||
rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
|
||||
pipe_resource_reference(&cb.buffer, NULL);
|
||||
}
|
||||
|
||||
/* On evergreen we only need to store the buffer size for TXQ */
|
||||
static void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type)
|
||||
{
|
||||
struct r600_textures_info *samplers = &rctx->samplers[shader_type];
|
||||
int bits;
|
||||
uint32_t array_size;
|
||||
struct pipe_constant_buffer cb;
|
||||
int i;
|
||||
|
||||
if (!samplers->views.dirty_buffer_constants)
|
||||
return;
|
||||
|
||||
samplers->views.dirty_buffer_constants = FALSE;
|
||||
|
||||
bits = util_last_bit(samplers->views.enabled_mask);
|
||||
array_size = bits * sizeof(uint32_t) * 4;
|
||||
samplers->buffer_constants = realloc(samplers->buffer_constants, array_size);
|
||||
memset(samplers->buffer_constants, 0, array_size);
|
||||
for (i = 0; i < bits; i++)
|
||||
if (samplers->views.enabled_mask & (1 << i))
|
||||
samplers->buffer_constants[i] = samplers->views.views[i]->base.texture->width0 / util_format_get_blocksize(samplers->views.views[i]->base.format);
|
||||
|
||||
cb.buffer = NULL;
|
||||
cb.user_buffer = samplers->buffer_constants;
|
||||
cb.buffer_offset = 0;
|
||||
cb.buffer_size = array_size;
|
||||
rctx->context.set_constant_buffer(&rctx->context, shader_type, R600_BUFFER_INFO_CONST_BUFFER, &cb);
|
||||
pipe_resource_reference(&cb.buffer, NULL);
|
||||
}
|
||||
|
||||
static void r600_setup_txq_cube_array_constants(struct r600_context *rctx, int shader_type)
|
||||
{
|
||||
struct r600_textures_info *samplers = &rctx->samplers[shader_type];
|
||||
|
|
@ -1090,6 +1178,21 @@ static bool r600_update_derived_state(struct r600_context *rctx)
|
|||
if (ps_dirty)
|
||||
r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
|
||||
|
||||
/* on R600 we stuff masks + txq info into one constant buffer */
|
||||
/* on evergreen we only need a txq info one */
|
||||
if (rctx->chip_class < EVERGREEN) {
|
||||
if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
|
||||
r600_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
|
||||
if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
|
||||
r600_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
|
||||
} else {
|
||||
if (rctx->ps_shader && rctx->ps_shader->current->shader.uses_tex_buffers)
|
||||
eg_setup_buffer_constants(rctx, PIPE_SHADER_FRAGMENT);
|
||||
if (rctx->vs_shader && rctx->vs_shader->current->shader.uses_tex_buffers)
|
||||
eg_setup_buffer_constants(rctx, PIPE_SHADER_VERTEX);
|
||||
}
|
||||
|
||||
|
||||
if (rctx->ps_shader && rctx->ps_shader->current->shader.has_txq_cube_array_z_comp)
|
||||
r600_setup_txq_cube_array_constants(rctx, PIPE_SHADER_FRAGMENT);
|
||||
if (rctx->vs_shader && rctx->vs_shader->current->shader.has_txq_cube_array_z_comp)
|
||||
|
|
|
|||
|
|
@ -912,18 +912,26 @@ void r600_init_surface_functions(struct r600_context *r600)
|
|||
r600->context.surface_destroy = r600_surface_destroy;
|
||||
}
|
||||
|
||||
static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
|
||||
const unsigned char *swizzle_view)
|
||||
unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format,
|
||||
const unsigned char *swizzle_view,
|
||||
boolean vtx)
|
||||
{
|
||||
unsigned i;
|
||||
unsigned char swizzle[4];
|
||||
unsigned result = 0;
|
||||
const uint32_t swizzle_shift[4] = {
|
||||
const uint32_t tex_swizzle_shift[4] = {
|
||||
16, 19, 22, 25,
|
||||
};
|
||||
const uint32_t vtx_swizzle_shift[4] = {
|
||||
3, 6, 9, 12,
|
||||
};
|
||||
const uint32_t swizzle_bit[4] = {
|
||||
0, 1, 2, 3,
|
||||
};
|
||||
const uint32_t *swizzle_shift = tex_swizzle_shift;
|
||||
|
||||
if (vtx)
|
||||
swizzle_shift = vtx_swizzle_shift;
|
||||
|
||||
if (swizzle_view) {
|
||||
util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle);
|
||||
|
|
@ -977,7 +985,7 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen,
|
|||
};
|
||||
desc = util_format_description(format);
|
||||
|
||||
word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view);
|
||||
word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view, FALSE);
|
||||
|
||||
/* Colorspace (return non-RGB formats directly). */
|
||||
switch (desc->colorspace) {
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue