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agx: Allow 64-bit memory regs

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The mask is based on the format, which can be at most 32-bits per channel. So if
we have 64-bit loads/stores we're still using a 32-bit format with double the
bits set in the mask. This will fix validation fails with spilling.

No shader-db changes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24635>
This commit is contained in:
Alyssa Rosenzweig 2023-08-01 07:26:03 -04:00 • committed by Marge Bot
parent d0b966cb10
commit d2224544d6
2 changed files with 7 additions and 4 deletions
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3
src/asahi/compiler/agx_pack.c
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@ -157,10 +157,9 @@ agx_pack_pbe_lod(agx_index index, bool *flag)
static unsigned static unsigned
agx_pack_memory_reg(agx_index index, bool *flag) agx_pack_memory_reg(agx_index index, bool *flag)
{ {
assert(index.size == AGX_SIZE_16 || index.size == AGX_SIZE_32);
assert_register_is_aligned(index); assert_register_is_aligned(index);
*flag = (index.size == AGX_SIZE_32); *flag = (index.size >= AGX_SIZE_32);
return index.value; return index.value;
} }

8
src/asahi/compiler/agx_register_allocate.c
View file

@ -56,7 +56,10 @@ agx_write_registers(const agx_instr *I, unsigned d)
case AGX_OPCODE_DEVICE_LOAD: case AGX_OPCODE_DEVICE_LOAD:
case AGX_OPCODE_LOCAL_LOAD: case AGX_OPCODE_LOCAL_LOAD:
case AGX_OPCODE_LD_TILE: case AGX_OPCODE_LD_TILE:
return util_bitcount(I->mask) * size; /* Can write 16-bit or 32-bit. Anything logically 64-bit is already
* expanded to 32-bit in the mask.
*/
return util_bitcount(I->mask) * MIN2(size, 2);
case AGX_OPCODE_LDCF: case AGX_OPCODE_LDCF:
return 6; return 6;
@ -215,8 +218,9 @@ agx_read_registers(const agx_instr *I, unsigned s)
case AGX_OPCODE_DEVICE_STORE: case AGX_OPCODE_DEVICE_STORE:
case AGX_OPCODE_LOCAL_STORE: case AGX_OPCODE_LOCAL_STORE:
case AGX_OPCODE_ST_TILE: case AGX_OPCODE_ST_TILE:
/* See agx_write_registers */
if (s == 0) if (s == 0)
return util_bitcount(I->mask) * size; return util_bitcount(I->mask) * MIN2(size, 2);
else else
return size; return size;