From d200f458751ad84aaec6015467bc8ee4efe69ad3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Tue, 13 Apr 2021 17:21:56 +0200 Subject: [PATCH] Use explicit break instead of fall-through to break-only case clang generates a warning if there's no explicit break or fall-through annotation. The latter would be kind of silly in this case, and not robust against any future changes turning the fall-through invalid. Reviewed-by: Eric Anholt Reviewed-by: Juan A. Suarez Part-of: --- src/amd/compiler/aco_insert_waitcnt.cpp | 1 + src/amd/compiler/aco_validate.cpp | 2 ++ src/broadcom/qpu/qpu_pack.c | 1 + src/broadcom/qpu/tests/qpu_disasm.c | 1 + src/freedreno/vulkan/tu_descriptor_set.c | 1 + src/freedreno/vulkan/tu_image.c | 1 + src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c | 1 + src/gallium/drivers/etnaviv/etnaviv_compiler_nir_ra.c | 1 + src/gallium/drivers/iris/iris_state.c | 1 + src/gallium/drivers/lima/ir/pp/codegen.c | 1 + src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c | 1 + src/intel/compiler/brw_eu_emit.c | 1 + 12 files changed, 13 insertions(+) diff --git a/src/amd/compiler/aco_insert_waitcnt.cpp b/src/amd/compiler/aco_insert_waitcnt.cpp index fdb74cbd9e5..b1879d61ac2 100644 --- a/src/amd/compiler/aco_insert_waitcnt.cpp +++ b/src/amd/compiler/aco_insert_waitcnt.cpp @@ -706,6 +706,7 @@ void gen(Instruction* instr, wait_ctx& ctx) if (instr->opcode == aco_opcode::s_sendmsg || instr->opcode == aco_opcode::s_sendmsghalt) update_counters(ctx, event_sendmsg); + break; } default: break; diff --git a/src/amd/compiler/aco_validate.cpp b/src/amd/compiler/aco_validate.cpp index 5fe6c58dc8d..bd77c0c3445 100644 --- a/src/amd/compiler/aco_validate.cpp +++ b/src/amd/compiler/aco_validate.cpp @@ -585,6 +585,7 @@ bool validate_subdword_operand(chip_class chip, const aco_ptr& inst case aco_opcode::global_store_short_d16_hi: if (byte == 2 && index == 2) return true; + break; default: break; } @@ -663,6 +664,7 @@ unsigned get_subdword_bytes_written(Program *program, const aco_ptr case aco_opcode::v_interp_p2_f16: if (chip >= GFX9) return 2; + break; default: break; } diff --git a/src/broadcom/qpu/qpu_pack.c b/src/broadcom/qpu/qpu_pack.c index 7502bbfb9d6..e50839f719f 100644 --- a/src/broadcom/qpu/qpu_pack.c +++ b/src/broadcom/qpu/qpu_pack.c @@ -1452,6 +1452,7 @@ v3d_qpu_instr_pack_branch(const struct v3d_device_info *devinfo, *packed_instr |= QPU_SET_FIELD(instr->branch.offset >> 24, VC5_QPU_BRANCH_ADDR_HIGH); + break; default: break; } diff --git a/src/broadcom/qpu/tests/qpu_disasm.c b/src/broadcom/qpu/tests/qpu_disasm.c index 5922b409aa8..e6b1918b8f0 100644 --- a/src/broadcom/qpu/tests/qpu_disasm.c +++ b/src/broadcom/qpu/tests/qpu_disasm.c @@ -162,6 +162,7 @@ main(int argc, char **argv) &instr.alu.add.b); swap_pack(&instr.alu.add.a_unpack, &instr.alu.add.b_unpack); + break; default: break; } diff --git a/src/freedreno/vulkan/tu_descriptor_set.c b/src/freedreno/vulkan/tu_descriptor_set.c index 34d9733a838..4a89271a908 100644 --- a/src/freedreno/vulkan/tu_descriptor_set.c +++ b/src/freedreno/vulkan/tu_descriptor_set.c @@ -527,6 +527,7 @@ tu_CreateDescriptorPool(VkDevice _device, case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC: case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC: dynamic_count += pCreateInfo->pPoolSizes[i].descriptorCount; + break; default: break; } diff --git a/src/freedreno/vulkan/tu_image.c b/src/freedreno/vulkan/tu_image.c index 1de7f90dc62..5e323f8627c 100644 --- a/src/freedreno/vulkan/tu_image.c +++ b/src/freedreno/vulkan/tu_image.c @@ -145,6 +145,7 @@ tu6_texswiz(const VkComponentMapping *comps, swiz[1] = A6XX_TEX_ZERO; } } + break; default: break; } diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c index 88c22819184..6d28fee391e 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c @@ -614,6 +614,7 @@ emit_instr(struct etna_compile *c, nir_instr * instr) break; case nir_instr_type_jump: assert(nir_instr_is_last(instr)); + break; case nir_instr_type_load_const: case nir_instr_type_ssa_undef: case nir_instr_type_deref: diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_ra.c b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_ra.c index fef982c9bf0..f97f796a53e 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_ra.c +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir_ra.c @@ -154,6 +154,7 @@ etna_ra_assign(struct etna_compile *c, nir_shader *shader) case nir_op_fcos: assert(dest->is_ssa); comp = REG_CLASS_VIRT_VEC2T; + break; default: break; } diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index b42b1136559..6ad47bff8a7 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -4086,6 +4086,7 @@ iris_emit_sbe_swiz(struct iris_batch *batch, attr->ConstantSource = PRIM_ID; continue; } + break; default: break; diff --git a/src/gallium/drivers/lima/ir/pp/codegen.c b/src/gallium/drivers/lima/ir/pp/codegen.c index dc5c02245f7..47ceb183677 100644 --- a/src/gallium/drivers/lima/ir/pp/codegen.c +++ b/src/gallium/drivers/lima/ir/pp/codegen.c @@ -541,6 +541,7 @@ static void ppir_codegen_encode_combine(ppir_node *node, void *code) default: break; } + break; } default: break; diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c index 38c6d15f245..3a78b519127 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c +++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c @@ -1085,6 +1085,7 @@ store_dest(struct ntv_context *ctx, nir_dest *dest, SpvId result, nir_alu_type t switch (nir_alu_type_get_base_type(type)) { case nir_type_bool: assert("bool should have bit-size 1"); + break; case nir_type_uint: break; /* nothing to do! */ diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 3f2c17d30d9..211fa4c9633 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -2914,6 +2914,7 @@ brw_find_next_block_end(struct brw_codegen *p, int start_offset) case BRW_OPCODE_HALT: if (depth == 0) return offset; + break; default: break; }