From d1ff453a0dfdbcc9d23ad1992487530bcab9994d Mon Sep 17 00:00:00 2001 From: Karol Herbst Date: Mon, 25 Apr 2022 22:21:16 +0200 Subject: [PATCH] nv50/nir: align tlsspace to 0x10 nvc0 aligns to 0x10 in setting up its rogram header, but nv50 TLS allocation expects the incoming value to be aligned already (like TGSI always did). Avoids regression in KHR-GL33.shaders.arrays.declaration.dynamic_expression_array_access_* with the nir backend. Reviewed-by: Emma Anholt Part-of: --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp index 0cd0bfab8d5..2895c2bac4a 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp @@ -1301,7 +1301,7 @@ Converter::storeTo(nir_intrinsic_instr *insn, DataFile file, operation op, bool Converter::parseNIR() { - info_out->bin.tlsSpace = nir->scratch_size; + info_out->bin.tlsSpace = ALIGN(nir->scratch_size, 0x10); info_out->io.clipDistances = nir->info.clip_distance_array_size; info_out->io.cullDistances = nir->info.cull_distance_array_size; info_out->io.layer_viewport_relative = nir->info.layer_viewport_relative;