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radeonsi: clear PIPE_IMAGE_ACCESS_WRITE when it's invalid to be on the safe side

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Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-11-24 00:19:56 +01:00
parent e3c0a5b6e8
commit d1f65e5e99
1 changed files with 10 additions and 0 deletions
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10
src/gallium/drivers/radeonsi/si_descriptors.c
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@ -688,6 +688,16 @@ static void si_set_shader_image_desc(struct si_context *ctx,
unsigned level = view->u.tex.level; unsigned level = view->u.tex.level;
unsigned width, height, depth, hw_level; unsigned width, height, depth, hw_level;
bool uses_dcc = vi_dcc_enabled(tex, level); bool uses_dcc = vi_dcc_enabled(tex, level);
unsigned access = view->access;
/* Clear the write flag when writes can't occur.
* Note that DCC_DECOMPRESS for MSAA doesn't work in some cases,
* so we don't wanna trigger it.
*/
if (tex->is_depth || tex->resource.b.b.nr_samples >= 2) {
assert(!"Z/S and MSAA image stores are not supported");
access &= ~PIPE_IMAGE_ACCESS_WRITE;
}
assert(!tex->is_depth); assert(!tex->is_depth);
assert(tex->fmask.size == 0); assert(tex->fmask.size == 0);