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brw: Add EU assembler support for float8

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Decode logic in Gfx12+ has become complex with the new types, so Caio
suggested that we move to the table like other gens.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39007>
This commit is contained in:
Sushma Venkatesh Reddy 2025-07-02 23:08:14 +00:00 • committed by Marge Bot
parent 0088aae481
commit d1d4e3d530
6 changed files with 74 additions and 20 deletions
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2
src/intel/compiler/brw/brw_eu_validate.c
View file

@ -387,6 +387,8 @@ execution_type_for_type(enum brw_reg_type type)
case BRW_TYPE_DF:
case BRW_TYPE_F:
case BRW_TYPE_HF:
case BRW_TYPE_BF8:
case BRW_TYPE_HF8:
return type;
case BRW_TYPE_VF:

6
src/intel/compiler/brw/brw_gram.y
View file

@ -358,8 +358,8 @@ i965_asm_set_instruction_options(struct brw_codegen *p,
%token <integer> TYPE_D TYPE_UD
%token <integer> TYPE_Q TYPE_UQ
%token <integer> TYPE_V TYPE_UV
%token <integer> TYPE_F TYPE_HF
%token <integer> TYPE_BF
%token <integer> TYPE_F TYPE_HF TYPE_HF8
%token <integer> TYPE_BF TYPE_BF8
%token <integer> TYPE_DF
%token <integer> TYPE_VF
@ -1872,6 +1872,8 @@ reg_type:
| TYPE_Q { $$ = BRW_TYPE_Q; }
| TYPE_HF { $$ = BRW_TYPE_HF; }
| TYPE_BF { $$ = BRW_TYPE_BF; }
| TYPE_HF8 { $$ = BRW_TYPE_HF8; }
| TYPE_BF8 { $$ = BRW_TYPE_BF8; }
;
imm_type:

2
src/intel/compiler/brw/brw_lex.l
View file

@ -302,10 +302,12 @@ BranchCtrl { return BRANCH_CTRL; }
/* data types */
:?B { return TYPE_B; }
:?BF { return TYPE_BF; }
:?BF8 { return TYPE_BF8; }
:?D { return TYPE_D; }
:?DF { return TYPE_DF; }
:?F { return TYPE_F; }
:?HF { return TYPE_HF; }
:?HF8 { return TYPE_HF8; }
:?Q { return TYPE_Q; }
:?UB { return TYPE_UB; }
:?UD { return TYPE_UD; }

61
src/intel/compiler/brw/brw_reg_type.c
View file

@ -46,6 +46,11 @@ brw_type_encode(const struct intel_device_info *devinfo,
: devinfo->has_64bit_float))
return INVALID_HW_REG_TYPE;
if (brw_type_is_float_or_bfloat(type) &&
brw_type_size_bits(type) == 8 &&
!devinfo->has_fp8)
return INVALID_HW_REG_TYPE;
if (brw_type_is_bfloat(type) && !devinfo->has_bfloat16)
return INVALID_HW_REG_TYPE;
@ -53,6 +58,11 @@ brw_type_encode(const struct intel_device_info *devinfo,
if (brw_type_is_vector_imm(type))
return type & ~(BRW_TYPE_VECTOR | BRW_TYPE_SIZE_MASK);
if (type == BRW_TYPE_BF8)
return 0b1000;
if (type == BRW_TYPE_HF8)
return 0b1100;
return type & (BRW_TYPE_BASE_MASK | BRW_TYPE_SIZE_MASK);
} else if (devinfo->ver >= 11) {
if (brw_type_is_vector_imm(type)) {
@ -117,18 +127,45 @@ brw_type_decode(const struct intel_device_info *devinfo,
return BRW_TYPE_INVALID;
if (devinfo->ver >= 12) {
enum brw_reg_type t = (enum brw_reg_type) hw_type;
if (brw_type_size_bits(t) == 8) {
if (brw_type_is_float(t))
return file == IMM ? BRW_TYPE_VF : BRW_TYPE_INVALID;
else if (file == IMM)
return (t & BRW_TYPE_BASE_SINT) ? BRW_TYPE_V : BRW_TYPE_UV;
static const enum brw_reg_type tbl[16] = {
[0b0000] = BRW_TYPE_UB, /* or UV */
[0b0001] = BRW_TYPE_UW,
[0b0010] = BRW_TYPE_UD,
[0b0011] = BRW_TYPE_UQ,
[0b0100] = BRW_TYPE_B, /* or V */
[0b0101] = BRW_TYPE_W,
[0b0110] = BRW_TYPE_D,
[0b0111] = BRW_TYPE_Q,
[0b1000] = BRW_TYPE_BF8, /* or VF */
[0b1001] = BRW_TYPE_HF,
[0b1010] = BRW_TYPE_F,
[0b1011] = BRW_TYPE_DF,
[0b1100] = BRW_TYPE_HF8,
[0b1101] = BRW_TYPE_BF,
[0b1110] = BRW_TYPE_INVALID,
[0b1111] = BRW_TYPE_INVALID,
};
enum brw_reg_type t = tbl[hw_type];
if (file == IMM) {
switch (t) {
case BRW_TYPE_UB: return BRW_TYPE_UV;
case BRW_TYPE_B: return BRW_TYPE_V;
case BRW_TYPE_BF8: return BRW_TYPE_VF;
case BRW_TYPE_HF8: return BRW_TYPE_VF;
default: break;
}
}
if (brw_type_is_bfloat(t) && !devinfo->has_bfloat16)
if ((t == BRW_TYPE_HF8 || t == BRW_TYPE_BF8) &&
!devinfo->has_fp8)
return BRW_TYPE_INVALID;
if (brw_type_is_float_or_bfloat(t) && brw_type_size_bits(t) < 16)
if (t == BRW_TYPE_BF && !devinfo->has_bfloat16)
return BRW_TYPE_INVALID;
return t;
} else if (devinfo->ver >= 11) {
static const enum brw_reg_type tbl[] = {
[0] = BRW_TYPE_UD,
@ -197,6 +234,10 @@ brw_type_encode_for_3src(const struct intel_device_info *devinfo,
{
if (brw_type_is_bfloat(type) && !devinfo->has_bfloat16)
return INVALID_HW_REG_TYPE;
if (brw_type_is_float_or_bfloat(type) &&
brw_type_size_bits(type) == 8 &&
!devinfo->has_fp8)
return INVALID_HW_REG_TYPE;
if (devinfo->ver >= 12) {
/* size mask and SINT type bit match exactly */
@ -292,9 +333,11 @@ brw_data_type_encode(const struct intel_device_info *devinfo,
[BRW_TYPE_W] = { BRW_TYPE_INT_W },
[BRW_TYPE_D] = { BRW_TYPE_INT_D },
[BRW_TYPE_Q] = { BRW_TYPE_INT_Q },
[BRW_TYPE_HF8] = { BRW_TYPE_FLOAT_HF8 },
[BRW_TYPE_HF] = { BRW_TYPE_FLOAT_HF },
[BRW_TYPE_F] = { BRW_TYPE_FLOAT_F },
[BRW_TYPE_DF] = { BRW_TYPE_FLOAT_DF },
[BRW_TYPE_BF8] = { BRW_TYPE_FLOAT_BF8 },
[BRW_TYPE_BF] = { BRW_TYPE_FLOAT_BF },
};
@ -328,9 +371,11 @@ brw_data_type_decode(const struct intel_device_info *devinfo,
},
[1 /* float exec_type */] = {
[0 ... 7] = BRW_TYPE_INVALID,
[BRW_TYPE_FLOAT_BF8] = BRW_TYPE_BF8,
[BRW_TYPE_FLOAT_HF] = BRW_TYPE_HF,
[BRW_TYPE_FLOAT_F] = BRW_TYPE_F,
[BRW_TYPE_FLOAT_DF] = BRW_TYPE_DF,
[BRW_TYPE_FLOAT_HF8] = BRW_TYPE_HF8,
[BRW_TYPE_FLOAT_BF] = BRW_TYPE_BF,
},
};

22
src/intel/compiler/brw/test_eu_validate.cpp
View file

@ -436,16 +436,18 @@ TEST_P(validation_test, invalid_type_encoding_3src_a1)
bool expected_result;
} test_case[] = {
#define E(x) ((unsigned)BRW_ALIGN1_3SRC_EXEC_TYPE_##x)
{ BRW_TYPE_DF, E(FLOAT), devinfo.has_64bit_float },
{ BRW_TYPE_F, E(FLOAT), true },
{ BRW_TYPE_HF, E(FLOAT), true },
{ BRW_TYPE_Q, E(INT), devinfo.has_64bit_int },
{ BRW_TYPE_UQ, E(INT), devinfo.has_64bit_int },
{ BRW_TYPE_D, E(INT), true },
{ BRW_TYPE_UD, E(INT), true },
{ BRW_TYPE_W, E(INT), true },
{ BRW_TYPE_UW, E(INT), true },
{ BRW_TYPE_BF, E(FLOAT), devinfo.has_bfloat16 },
{ BRW_TYPE_DF, E(FLOAT), devinfo.has_64bit_float },
{ BRW_TYPE_F, E(FLOAT), true },
{ BRW_TYPE_HF, E(FLOAT), true },
{ BRW_TYPE_Q, E(INT), devinfo.has_64bit_int },
{ BRW_TYPE_UQ, E(INT), devinfo.has_64bit_int },
{ BRW_TYPE_D, E(INT), true },
{ BRW_TYPE_UD, E(INT), true },
{ BRW_TYPE_W, E(INT), true },
{ BRW_TYPE_UW, E(INT), true },
{ BRW_TYPE_BF, E(FLOAT), devinfo.has_bfloat16 },
{ BRW_TYPE_BF8, E(FLOAT), devinfo.has_fp8 },
{ BRW_TYPE_HF8, E(FLOAT), devinfo.has_fp8 },
/* There are no ternary instructions that can operate on B-type sources
* on Gfx11-12. Src1/Src2 cannot be B-typed either.

1
src/intel/dev/intel_device_info.py
View file

@ -284,6 +284,7 @@ Struct("intel_device_info",
Member("bool", "has_64bit_float_via_math_pipe", compiler_field=True),
Member("bool", "has_64bit_int", compiler_field=True),
Member("bool", "has_bfloat16", compiler_field=True),
Member("bool", "has_fp8", compiler_field=True),
Member("bool", "has_integer_dword_mul", compiler_field=True),
Member("bool", "has_systolic", compiler_field=True),
Member("bool", "supports_simd16_3src", compiler_field=True),