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i965/fs: Optimize gl_FrontFacing calculation on Gen6+.

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total instructions in shared programs: 4288650 -> 4282838 (-0.14%)
instructions in affected programs:     595018 -> 589206 (-0.98%)

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
This commit is contained in:
Matt Turner 2014-08-10 09:04:49 -07:00
parent 2e51dc838b
commit d1c43ed487
1 changed files with 15 additions and 6 deletions
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21
src/mesa/drivers/dri/i965/brw_fs.cpp
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@ -1188,13 +1188,22 @@ fs_visitor::emit_frontfacing_interpolation(ir_variable *ir)
{ {
fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type); fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
/* The frontfacing comes in as a bit in the thread payload. */
if (brw->gen >= 6) { if (brw->gen >= 6) {
emit(BRW_OPCODE_SHL, *reg, /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)), * a boolean result from this (~0/true or 0/false).
fs_reg(16)); *
emit(BRW_OPCODE_NOT, *reg, *reg); * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
emit(BRW_OPCODE_ASR, *reg, *reg, fs_reg(31)); * this task in only one instruction:
* - a negation source modifier will flip the bit; and
* - a W -> D type conversion will sign extend the bit into the high
* word of the destination.
*
* An ASR 15 fills the low word of the destination.
*/
fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
g0.negate = true;
emit(ASR(*reg, g0, fs_reg(15)));
} else { } else {
struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD); struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD);
/* bit 31 is "primitive is back face", so checking < (1 << 31) gives /* bit 31 is "primitive is back face", so checking < (1 << 31) gives