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brw: handle non-GRF aligned pushed UBO masking

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Right now all the drivers align push data to GRF (32B pre Xe2, 64B
post Xe2) but the push constant delivery mechanism can actually pack
32B ranges so alignment is not required.

Off course we need the push UBO masking to deal with unaligned pushed
ranges.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Calder Young <cgiacun@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35160>
This commit is contained in:
Lionel Landwerlin 2026-01-13 11:57:09 +02:00 • committed by Marge Bot
parent c1c9048dbf
commit d1a1e98e4e
1 changed files with 9 additions and 1 deletions
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10
src/intel/compiler/brw/brw_shader.cpp
View file

@ -586,7 +586,15 @@ brw_shader::assign_curb_setup()
ubld_mask.CMP(mask_reg, byte_offset(mask, i), offset_reg, BRW_CONDITIONAL_G);
for (unsigned and_length; grf < mask_end; grf += and_length) {
and_length = 1u << (util_last_bit(MIN2(grf_end - grf, max_grf_writes)) - 1);
/* We can't have a destination/source register spanning more
* than 2 GRFs which would be the case on Xe2+ if we try to
* mask a payload register not aligned to 64B with a SIMD32
* instruction. In such case just reduce the SIMDness for the
* unaligned masking.
*/
unsigned max_write = grf % reg_unit(devinfo) != 0 ? max_grf_writes / 2 : max_grf_writes;
and_length = 1u << (util_last_bit(MIN2(grf_end - grf, max_write)) - 1);
if (!(want_zero & BITFIELD64_RANGE(grf - grf_start, and_length)))
continue;