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freedreno/a6xx: Extract out GMEM cache helper
Extract out a helper to calculate placement of various caches that live in GMEM. Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39052>
This commit is contained in:
Rob Clark
parent
ebf1454410
commit
d197ea37d1
3 changed files with 127 additions and 104 deletions
121
src/freedreno/common/fd6_gmem_cache.h
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121
src/freedreno/common/fd6_gmem_cache.h
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@ -0,0 +1,121 @@
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its susidiaries.
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* SPDX-License-Identifier: MIT
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*/
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#ifndef FD6_GMEM_CACHE_H
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#define FD6_GMEM_CACHE_H
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#include <stdint.h>
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#include "common/freedreno_dev_info.h"
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/* Offset within GMEM of various "non-GMEM" things that GMEM is used to
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* cache. These offsets differ for gmem vs sysmem rendering (in sysmem
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* mode, the entire GMEM can be used)
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*/
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struct fd6_gmem_config {
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/* Color/depth CCU cache: */
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uint32_t color_ccu_offset;
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uint32_t depth_ccu_offset;
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/* Vertex attrib cache (a750+): */
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uint32_t vpc_attr_buf_size;
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uint32_t vpc_attr_buf_offset;
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/* Vertex position cache (a8xx+): */
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uint32_t vpc_pos_buf_size;
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uint32_t vpc_pos_buf_offset;
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uint32_t vpc_bv_pos_buf_size;
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uint32_t vpc_bv_pos_buf_offset;
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/* see enum a6xx_ccu_cache_size */
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uint32_t depth_cache_fraction;
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uint32_t color_cache_fraction;
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uint32_t depth_cache_size;
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uint32_t color_cache_size;
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};
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static inline unsigned
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__calc_gmem_cache_offsets(const struct fd_dev_info *info, unsigned offset,
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struct fd6_gmem_config *config)
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{
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unsigned num_ccu = info->num_ccu;
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/* This seems not to be load bearing, but keeping it for now to match blob: */
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if (info->chip >= 8)
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offset -= 0x78000;
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config->vpc_bv_pos_buf_offset = offset - (num_ccu * config->vpc_bv_pos_buf_size);
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offset = config->vpc_bv_pos_buf_offset;
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config->vpc_attr_buf_offset = offset - (num_ccu * config->vpc_attr_buf_size);
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offset = config->vpc_attr_buf_offset;
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config->vpc_pos_buf_offset = offset - (num_ccu * config->vpc_pos_buf_size);
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offset = config->vpc_pos_buf_offset;
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config->color_ccu_offset = offset - (num_ccu * config->color_cache_size);
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offset = config->color_ccu_offset;
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config->depth_ccu_offset = offset - (num_ccu * config->depth_cache_size);
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offset = config->depth_ccu_offset;
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return offset;
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}
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static inline unsigned
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fd6_calc_gmem_cache_offsets(const struct fd_dev_info *info, unsigned gmemsize_bytes,
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struct fd6_gmem_config *gmem, struct fd6_gmem_config *sysmem)
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{
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uint32_t depth_cache_size =
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info->num_ccu * info->props.sysmem_per_ccu_depth_cache_size;
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uint32_t color_cache_size =
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(info->num_ccu * info->props.sysmem_per_ccu_color_cache_size);
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uint32_t color_cache_size_gmem =
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color_cache_size /
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(1 << info->props.gmem_ccu_color_cache_fraction);
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sysmem->depth_ccu_offset = 0;
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sysmem->color_ccu_offset = sysmem->depth_ccu_offset + depth_cache_size;
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/* TODO we could unify gen7/gen8 setup.. gen7 is a subset.. */
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if (info->chip == 8) {
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gmem->depth_cache_fraction = info->props.gmem_ccu_depth_cache_fraction;
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gmem->depth_cache_size = info->props.gmem_per_ccu_depth_cache_size;
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gmem->color_cache_fraction = info->props.gmem_ccu_color_cache_fraction;
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gmem->color_cache_size = info->props.gmem_per_ccu_color_cache_size;
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gmem->vpc_attr_buf_size = info->props.gmem_vpc_attr_buf_size;
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gmem->vpc_pos_buf_size = info->props.gmem_vpc_pos_buf_size;
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gmem->vpc_bv_pos_buf_size = info->props.gmem_vpc_bv_pos_buf_size;
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sysmem->depth_cache_fraction = info->props.sysmem_ccu_depth_cache_fraction;
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sysmem->depth_cache_size = info->props.sysmem_per_ccu_depth_cache_size;
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sysmem->color_cache_fraction = info->props.sysmem_ccu_color_cache_fraction;
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sysmem->color_cache_size = info->props.sysmem_per_ccu_color_cache_size;
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sysmem->vpc_attr_buf_size = info->props.sysmem_vpc_attr_buf_size;
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sysmem->vpc_pos_buf_size = info->props.sysmem_vpc_pos_buf_size;
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sysmem->vpc_bv_pos_buf_size = info->props.sysmem_vpc_bv_pos_buf_size;
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__calc_gmem_cache_offsets(info, gmemsize_bytes, sysmem);
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return __calc_gmem_cache_offsets(info, gmemsize_bytes, gmem);
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} else if (info->props.has_gmem_vpc_attr_buf) {
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sysmem->vpc_attr_buf_size = info->props.sysmem_vpc_attr_buf_size;
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sysmem->vpc_attr_buf_offset = sysmem->color_ccu_offset + color_cache_size;
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gmem->vpc_attr_buf_size = info->props.gmem_vpc_attr_buf_size;
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gmem->vpc_attr_buf_offset = gmemsize_bytes -
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(gmem->vpc_attr_buf_size * info->num_ccu);
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gmem->color_ccu_offset = gmem->vpc_attr_buf_offset - color_cache_size_gmem;
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return gmem->vpc_attr_buf_offset;
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} else {
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gmem->depth_ccu_offset = 0;
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gmem->color_ccu_offset = gmemsize_bytes - color_cache_size_gmem;
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return gmemsize_bytes;
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}
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}
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#endif /* FD6_GMEM_CACHE_H */
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@ -160,91 +160,17 @@ static const enum pc_di_primtype primtypes[] = {
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};
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/* clang-format on */
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static unsigned
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calc_gmem_cache_offsets(struct fd_screen *screen, struct fd6_gmem_config *config)
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{
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unsigned num_ccu = screen->info->num_ccu;
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/* Layout from end of gmem: */
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unsigned offset = screen->gmemsize_bytes;
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// ????
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offset -= 0x78000;
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config->vpc_bv_pos_buf_offset = offset - (num_ccu * config->vpc_bv_pos_buf_size);
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offset = config->vpc_bv_pos_buf_offset;
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config->vpc_attr_buf_offset = offset - (num_ccu * config->vpc_attr_buf_size);
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offset = config->vpc_attr_buf_offset;
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config->vpc_pos_buf_offset = offset - (num_ccu * config->vpc_pos_buf_size);
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offset = config->vpc_pos_buf_offset;
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config->color_ccu_offset = offset - (num_ccu * config->color_cache_size);
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offset = config->color_ccu_offset;
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config->depth_ccu_offset = offset - (num_ccu * config->depth_cache_size);
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offset = config->depth_ccu_offset;
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return offset;
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}
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void
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fd6_screen_init(struct pipe_screen *pscreen)
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{
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struct fd_screen *screen = fd_screen(pscreen);
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const struct fd_dev_info *info = screen->info;
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screen->max_rts = A6XX_MAX_RENDER_TARGETS;
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uint32_t depth_cache_size =
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screen->info->num_ccu * screen->info->props.sysmem_per_ccu_depth_cache_size;
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uint32_t color_cache_size =
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(screen->info->num_ccu * screen->info->props.sysmem_per_ccu_color_cache_size);
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uint32_t color_cache_size_gmem =
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color_cache_size /
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(1 << screen->info->props.gmem_ccu_color_cache_fraction);
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struct fd6_gmem_config *gmem = &screen->config_gmem;
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struct fd6_gmem_config *sysmem = &screen->config_sysmem;
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sysmem->depth_ccu_offset = 0;
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sysmem->color_ccu_offset = sysmem->depth_ccu_offset + depth_cache_size;
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/* TODO we could unify gen7/gen8 setup.. gen7 is a subset.. */
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if (info->chip == 8) {
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gmem->depth_cache_fraction = info->props.gmem_ccu_depth_cache_fraction;
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gmem->depth_cache_size = info->props.gmem_per_ccu_depth_cache_size;
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gmem->color_cache_fraction = info->props.gmem_ccu_color_cache_fraction;
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gmem->color_cache_size = info->props.gmem_per_ccu_color_cache_size;
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gmem->vpc_attr_buf_size = info->props.gmem_vpc_attr_buf_size;
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gmem->vpc_pos_buf_size = info->props.gmem_vpc_pos_buf_size;
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gmem->vpc_bv_pos_buf_size = info->props.gmem_vpc_bv_pos_buf_size;
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sysmem->depth_cache_fraction = info->props.sysmem_ccu_depth_cache_fraction;
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sysmem->depth_cache_size = info->props.sysmem_per_ccu_depth_cache_size;
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sysmem->color_cache_fraction = info->props.sysmem_ccu_color_cache_fraction;
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sysmem->color_cache_size = info->props.sysmem_per_ccu_color_cache_size;
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sysmem->vpc_attr_buf_size = info->props.sysmem_vpc_attr_buf_size;
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sysmem->vpc_pos_buf_size = info->props.sysmem_vpc_pos_buf_size;
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sysmem->vpc_bv_pos_buf_size = info->props.sysmem_vpc_bv_pos_buf_size;
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calc_gmem_cache_offsets(screen, sysmem);
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screen->gmemsize_bytes = calc_gmem_cache_offsets(screen, gmem);
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} else if (screen->info->props.has_gmem_vpc_attr_buf) {
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sysmem->vpc_attr_buf_size = screen->info->props.sysmem_vpc_attr_buf_size;
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sysmem->vpc_attr_buf_offset = sysmem->color_ccu_offset + color_cache_size;
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gmem->vpc_attr_buf_size = screen->info->props.gmem_vpc_attr_buf_size;
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gmem->vpc_attr_buf_offset = screen->gmemsize_bytes -
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(gmem->vpc_attr_buf_size * screen->info->num_ccu);
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gmem->color_ccu_offset = gmem->vpc_attr_buf_offset - color_cache_size_gmem;
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screen->gmemsize_bytes = gmem->vpc_attr_buf_offset;
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} else {
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gmem->depth_ccu_offset = 0;
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gmem->color_ccu_offset = screen->gmemsize_bytes - color_cache_size_gmem;
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}
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screen->gmemsize_bytes =
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fd6_calc_gmem_cache_offsets(screen->info, screen->gmemsize_bytes,
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&screen->config_gmem,
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&screen->config_sysmem);
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/* Currently only FB_READ forces GMEM path, mostly because we'd have to
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* deal with cmdstream patching otherwise..
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@ -23,6 +23,8 @@
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#include "util/u_memory.h"
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#include "util/u_queue.h"
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#include "common/fd6_gmem_cache.h"
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#include "freedreno_batch_cache.h"
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#include "freedreno_gmem.h"
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#include "freedreno_util.h"
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@ -48,32 +50,6 @@ enum fd_gmem_reason {
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FD_GMEM_FB_READ = BIT(5),
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};
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/* Offset within GMEM of various "non-GMEM" things that GMEM is used to
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* cache. These offsets differ for gmem vs sysmem rendering (in sysmem
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* mode, the entire GMEM can be used)
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*/
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struct fd6_gmem_config {
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/* Color/depth CCU cache: */
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uint32_t color_ccu_offset;
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uint32_t depth_ccu_offset;
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/* Vertex attrib cache (a750+): */
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uint32_t vpc_attr_buf_size;
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uint32_t vpc_attr_buf_offset;
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/* Vertex position cache (a8xx+): */
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uint32_t vpc_pos_buf_size;
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uint32_t vpc_pos_buf_offset;
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uint32_t vpc_bv_pos_buf_size;
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uint32_t vpc_bv_pos_buf_offset;
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/* see enum a6xx_ccu_cache_size */
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uint32_t depth_cache_fraction;
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uint32_t color_cache_fraction;
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uint32_t depth_cache_size;
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uint32_t color_cache_size;
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};
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struct fd_screen {
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struct pipe_screen base;
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