diff --git a/src/freedreno/common/freedreno_dev_info.h b/src/freedreno/common/freedreno_dev_info.h index c68983e91c4..79137efc51d 100644 --- a/src/freedreno/common/freedreno_dev_info.h +++ b/src/freedreno/common/freedreno_dev_info.h @@ -227,7 +227,6 @@ struct fd_dev_info { bool is_a702; struct { - uint32_t UCHE_CLIENT_PF; uint32_t PC_MODE_CNTL; uint32_t SP_DBG_ECO_CNTL; uint32_t RB_DBG_ECO_CNTL; diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py index 147c4aa0c5b..0d9edc141ae 100644 --- a/src/freedreno/common/freedreno_devices.py +++ b/src/freedreno/common/freedreno_devices.py @@ -468,7 +468,6 @@ add_gpus([ ubwc_swizzle = 0x7, macrotile_mode = 0, magic_regs = dict( - UCHE_CLIENT_PF = 0x00000004, PC_MODE_CNTL = 0xf, SP_DBG_ECO_CNTL = 0x0, RB_DBG_ECO_CNTL = 0x04100000, @@ -484,6 +483,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004], ], )) @@ -505,7 +505,6 @@ add_gpus([ highest_bank_bit = 14, macrotile_mode = 0, magic_regs = dict( - UCHE_CLIENT_PF = 0x00000004, PC_MODE_CNTL = 0x1f, SP_DBG_ECO_CNTL = 0x0, RB_DBG_ECO_CNTL = 0x04100000, @@ -521,6 +520,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x00108000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0x00000880], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00000430], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004], ], )) @@ -537,7 +537,6 @@ add_gpus([ wave_granularity = 2, fibers_per_sp = 128 * 16, magic_regs = dict( - UCHE_CLIENT_PF = 0x00000004, PC_MODE_CNTL = 0x1f, SP_DBG_ECO_CNTL = 0x01000000, RB_DBG_ECO_CNTL = 0x04100000, @@ -553,6 +552,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x01008000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00000400], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004], ], )) @@ -570,7 +570,6 @@ add_gpus([ wave_granularity = 2, fibers_per_sp = 128 * 2 * 16, magic_regs = dict( - # UCHE_CLIENT_PF = 0x00000004, PC_MODE_CNTL = 0x1f, SP_DBG_ECO_CNTL = 0x03000000, RB_DBG_ECO_CNTL = 0x04100000, @@ -605,7 +604,6 @@ add_gpus([ highest_bank_bit = 15, macrotile_mode = 0, magic_regs = dict( - UCHE_CLIENT_PF = 0x00000004, PC_MODE_CNTL = 0x1f, SP_DBG_ECO_CNTL = 0x0, RB_DBG_ECO_CNTL = 0x04100000, @@ -621,6 +619,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x00108000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0x00000880], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001430], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004], ], )) @@ -639,7 +638,6 @@ add_gpus([ highest_bank_bit = 15, macrotile_mode = 0, magic_regs = dict( - UCHE_CLIENT_PF = 0x00000004, PC_MODE_CNTL = 0x1f, SP_DBG_ECO_CNTL = 0x0, RB_DBG_ECO_CNTL = 0x04100000, @@ -655,6 +653,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x00008000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00000420], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004], ], )) @@ -673,7 +672,6 @@ add_gpus([ highest_bank_bit = 15, macrotile_mode = 0, magic_regs = dict( - UCHE_CLIENT_PF = 0x00000004, PC_MODE_CNTL = 0x1f, SP_DBG_ECO_CNTL = 0x0, RB_DBG_ECO_CNTL = 0x04100000, @@ -689,6 +687,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x00108000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001430], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004], ], )) @@ -706,7 +705,6 @@ add_gpus([ fibers_per_sp = 128 * 2 * 16, highest_bank_bit = 16, magic_regs = dict( - UCHE_CLIENT_PF = 0x00000004, PC_MODE_CNTL = 0x1f, SP_DBG_ECO_CNTL = 0x01000000, RB_DBG_ECO_CNTL = 0x04100000, @@ -723,6 +721,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x00108000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000004], ], )) @@ -746,7 +745,6 @@ add_gpus([ fibers_per_sp = 128 * 2 * 16, highest_bank_bit = 14, magic_regs = dict( - UCHE_CLIENT_PF = 0x00000084, PC_MODE_CNTL = 0x1f, SP_DBG_ECO_CNTL = 0x00000006, RB_DBG_ECO_CNTL = 0x04100000, @@ -762,6 +760,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x05008000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084], ], )) @@ -779,7 +778,6 @@ add_gpus([ fibers_per_sp = 128 * 2 * 16, highest_bank_bit = 16, magic_regs = dict( - UCHE_CLIENT_PF = 0x00000084, PC_MODE_CNTL = 0x1f, SP_DBG_ECO_CNTL = 0x01000000, RB_DBG_ECO_CNTL = 0x04100000, @@ -795,6 +793,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x05008000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084], ], )) @@ -812,7 +811,6 @@ add_gpus([ wave_granularity = 2, fibers_per_sp = 128 * 4 * 16, magic_regs = dict( - UCHE_CLIENT_PF = 0x00000084, PC_MODE_CNTL = 0x1f, SP_DBG_ECO_CNTL = 0x6, RB_DBG_ECO_CNTL = 0x04100000, @@ -828,6 +826,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x05008000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084], ], )) @@ -846,7 +845,6 @@ add_gpus([ fibers_per_sp = 128 * 2 * 16, highest_bank_bit = 16, magic_regs = dict( - UCHE_CLIENT_PF = 0x00000084, PC_MODE_CNTL = 0x1f, SP_DBG_ECO_CNTL = 0x1200000, RB_DBG_ECO_CNTL = 0x100000, @@ -863,6 +861,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x04c00000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084], ], )) @@ -895,7 +894,6 @@ add_gpus([ max_waves = 16, # has_early_preamble = True, # for VS/FS but not CS? magic_regs = dict( - UCHE_CLIENT_PF = 0x84, PC_MODE_CNTL = 0xf, SP_DBG_ECO_CNTL = 0x0, RB_DBG_ECO_CNTL = 0x100000, @@ -911,6 +909,7 @@ add_gpus([ [A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL, 0x8000], [A6XXRegs.REG_A6XX_GRAS_DBG_ECO_CNTL, 0], [A6XXRegs.REG_A6XX_SP_CHICKEN_BITS, 0x00001400], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084], ], )) @@ -1021,7 +1020,6 @@ a7xx_gen3 = A7XXProps( ) a730_magic_regs = dict( - UCHE_CLIENT_PF = 0x00000084, PC_MODE_CNTL = 0x0000003f, # 0x00001f1f in some tests SP_DBG_ECO_CNTL = 0x10000000, RB_DBG_ECO_CNTL = 0x00000000, @@ -1042,6 +1040,7 @@ a730_raw_magic_regs = [ [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00402400], [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00000000], [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00000000], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084], [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000], [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000040], [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00008000], @@ -1072,7 +1071,6 @@ a730_raw_magic_regs = [ ] a740_magic_regs = dict( - UCHE_CLIENT_PF = 0x00000084, # Blob uses 0x1f or 0x1f1f, however these values cause vertices # corruption in some tests. PC_MODE_CNTL = 0x0000003f, @@ -1096,6 +1094,7 @@ a740_raw_magic_regs = [ [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00400400], [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00430800], [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00000000], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084], [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000], [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000000], [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00000000], @@ -1177,7 +1176,6 @@ add_gpus([ wave_granularity = 2, fibers_per_sp = 128 * 2 * 16, magic_regs = dict( - UCHE_CLIENT_PF = 0x00000084, PC_MODE_CNTL = 0x0000001f, SP_DBG_ECO_CNTL = 0x10000000, RB_DBG_ECO_CNTL = 0x00000001, @@ -1197,6 +1195,7 @@ add_gpus([ [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00400400], [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00430800], [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00000000], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084], [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000], [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000000], [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00000000], @@ -1272,6 +1271,7 @@ add_gpus([ [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00400400], [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00430820], [A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00000000], + [A6XXRegs.REG_A6XX_UCHE_CLIENT_PF, 0x00000084], [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000], [A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000080], [A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00000000], @@ -1316,7 +1316,6 @@ add_gpus([ wave_granularity = 2, fibers_per_sp = 128 * 2 * 16, magic_regs = dict( - UCHE_CLIENT_PF = 0x00000084, # Blob uses 0x1f or 0x1f1f, however these values cause vertices # corruption in some tests. PC_MODE_CNTL = 0x0000003f, diff --git a/src/freedreno/vulkan/tu_cmd_buffer.cc b/src/freedreno/vulkan/tu_cmd_buffer.cc index 9c2d59da074..6f6cf61c8cd 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.cc +++ b/src/freedreno/vulkan/tu_cmd_buffer.cc @@ -1984,8 +1984,6 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs) tu_cs_emit_regs(cs, A6XX_HLSQ_SHARED_CONSTS(.enable = false)); tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_UNKNOWN_0E12, phys_dev->info->a6xx.magic.UCHE_UNKNOWN_0E12); - tu_cs_emit_write_reg(cs, REG_A6XX_UCHE_CLIENT_PF, - phys_dev->info->a6xx.magic.UCHE_CLIENT_PF); tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0); tu_cs_emit_regs(cs, A6XX_SP_MODE_CNTL(.constant_demotion_enable = true, .isammode = ISAMMODE_GL, diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc index 91744ef2527..cf7e77310bb 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_emit.cc @@ -882,7 +882,6 @@ fd6_emit_static_non_context_regs(struct fd_context *ctx, fd_cs &cs) ncrb.add(HLSQ_DBG_ECO_CNTL(CHIP, .dword = screen->info->a6xx.magic.HLSQ_DBG_ECO_CNTL)); ncrb.add(UCHE_UNKNOWN_0E12(CHIP, .dword = screen->info->a6xx.magic.UCHE_UNKNOWN_0E12)); - ncrb.add(UCHE_CLIENT_PF(CHIP, .dword = screen->info->a6xx.magic.UCHE_CLIENT_PF)); if (CHIP == A6XX) { ncrb.add(HLSQ_SHARED_CONSTS(CHIP));