diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index febe16e1f89..27c01937a15 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -3852,6 +3852,12 @@ enum anv_coarse_pixel_state { ANV_COARSE_PIXEL_STATE_ENABLED, }; +enum anv_depth_reg_mode { + ANV_DEPTH_REG_MODE_UNKNOWN = 0, + ANV_DEPTH_REG_MODE_HW_DEFAULT, + ANV_DEPTH_REG_MODE_D16_1X_MSAA, +}; + /** State tracking for graphics pipeline * * This has anv_cmd_pipeline_state as a base struct to track things which get @@ -3932,13 +3938,29 @@ struct anv_cmd_graphics_state { uint32_t n_occlusion_queries; - struct anv_gfx_dynamic_state dyn_state; -}; + /** + * Whether or not the gfx8 PMA fix is enabled. We ensure that, at the top + * of any command buffer it is disabled by disabling it in EndCommandBuffer + * and before invoking the secondary in ExecuteCommands. + */ + bool pma_fix_enabled; -enum anv_depth_reg_mode { - ANV_DEPTH_REG_MODE_UNKNOWN = 0, - ANV_DEPTH_REG_MODE_HW_DEFAULT, - ANV_DEPTH_REG_MODE_D16_1X_MSAA, + /** + * Whether or not we know for certain that HiZ is enabled for the current + * subpass. If, for whatever reason, we are unsure as to whether HiZ is + * enabled or not, this will be false. + */ + bool hiz_enabled; + + /** + * We ensure the registers for the gfx12 D16 fix are initialized at the + * first non-NULL depth stencil packet emission of every command buffer. + * For secondary command buffer execution, we transfer the state from the + * last command buffer to the primary (if known). + */ + enum anv_depth_reg_mode depth_reg_mode; + + struct anv_gfx_dynamic_state dyn_state; }; /** State tracking for compute pipeline @@ -4044,27 +4066,6 @@ struct anv_cmd_state { unsigned char surface_sha1s[MESA_VULKAN_SHADER_STAGES][20]; unsigned char push_sha1s[MESA_VULKAN_SHADER_STAGES][20]; - /** - * Whether or not the gfx8 PMA fix is enabled. We ensure that, at the top - * of any command buffer it is disabled by disabling it in EndCommandBuffer - * and before invoking the secondary in ExecuteCommands. - */ - bool pma_fix_enabled; - - /** - * Whether or not we know for certain that HiZ is enabled for the current - * subpass. If, for whatever reason, we are unsure as to whether HiZ is - * enabled or not, this will be false. - */ - bool hiz_enabled; - - /* We ensure the registers for the gfx12 D16 fix are initialized at the - * first non-NULL depth stencil packet emission of every command buffer. - * For secondary command buffer execution, we transfer the state from the - * last command buffer to the primary (if known). - */ - enum anv_depth_reg_mode depth_reg_mode; - /* The last auxiliary surface operation (or equivalent operation) provided * to genX(cmd_buffer_update_color_aux_op). */ diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index a71d4cf814c..ee049fef7c8 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -3623,8 +3623,8 @@ genX(CmdExecuteCommands)( container->perf_query_pool = secondary->perf_query_pool; #if INTEL_NEEDS_WA_1808121037 - if (secondary->state.depth_reg_mode != ANV_DEPTH_REG_MODE_UNKNOWN) - container->state.depth_reg_mode = secondary->state.depth_reg_mode; + if (secondary->state.gfx.depth_reg_mode != ANV_DEPTH_REG_MODE_UNKNOWN) + container->state.gfx.depth_reg_mode = secondary->state.gfx.depth_reg_mode; #endif container->state.gfx.viewport_set |= secondary->state.gfx.viewport_set; @@ -4842,7 +4842,7 @@ genX(cmd_buffer_emit_gfx12_depth_wa)(struct anv_cmd_buffer *cmd_buffer, const bool is_d16_1x_msaa = surf->format == ISL_FORMAT_R16_UNORM && surf->samples == 1; - switch (cmd_buffer->state.depth_reg_mode) { + switch (cmd_buffer->state.gfx.depth_reg_mode) { case ANV_DEPTH_REG_MODE_HW_DEFAULT: if (!is_d16_1x_msaa) return; @@ -4876,7 +4876,7 @@ genX(cmd_buffer_emit_gfx12_depth_wa)(struct anv_cmd_buffer *cmd_buffer, reg.HIZPlaneOptimizationdisablebitMask = true; } - cmd_buffer->state.depth_reg_mode = + cmd_buffer->state.gfx.depth_reg_mode = is_d16_1x_msaa ? ANV_DEPTH_REG_MODE_D16_1X_MSAA : ANV_DEPTH_REG_MODE_HW_DEFAULT; #endif @@ -5175,7 +5175,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer) if (info.depth_surf) genX(cmd_buffer_emit_gfx12_depth_wa)(cmd_buffer, info.depth_surf); - cmd_buffer->state.hiz_enabled = isl_aux_usage_has_hiz(info.hiz_usage); + cmd_buffer->state.gfx.hiz_enabled = isl_aux_usage_has_hiz(info.hiz_usage); } static void diff --git a/src/intel/vulkan/genX_gfx_state.c b/src/intel/vulkan/genX_gfx_state.c index 7d752777b3f..c8d46c44988 100644 --- a/src/intel/vulkan/genX_gfx_state.c +++ b/src/intel/vulkan/genX_gfx_state.c @@ -272,7 +272,7 @@ want_stencil_pma_fix(struct anv_cmd_buffer *cmd_buffer, * (3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL) && * 3DSTATE_DEPTH_BUFFER::HIZ Enable */ - if (!cmd_buffer->state.hiz_enabled) + if (!cmd_buffer->state.gfx.hiz_enabled) return false; /* We can't possibly know if HiZ is enabled without the depth attachment */ @@ -2645,10 +2645,10 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer *cmd_buffer, bool enable) if (!anv_cmd_buffer_is_render_queue(cmd_buffer)) return; - if (cmd_buffer->state.pma_fix_enabled == enable) + if (cmd_buffer->state.gfx.pma_fix_enabled == enable) return; - cmd_buffer->state.pma_fix_enabled = enable; + cmd_buffer->state.gfx.pma_fix_enabled = enable; /* According to the Broadwell PIPE_CONTROL documentation, software should * emit a PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set