From d146a31ee1a061fb815569f04e0780c7f99c310c Mon Sep 17 00:00:00 2001
From: Rob Clark <rob.clark@oss.qualcomm.com>
Date: Mon, 27 Oct 2025 07:47:56 -0700
Subject: [PATCH] ir3: Add mova .u bit

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38450>
---
 src/freedreno/ir3/ir3_parser.y   |  7 +++++--
 src/freedreno/ir3/tests/disasm.c |  3 +++
 src/freedreno/isa/ir3-cat1.xml   | 10 +++++++---
 3 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/src/freedreno/ir3/ir3_parser.y b/src/freedreno/ir3/ir3_parser.y
index ce87dd489dd..d0e1ffa7512 100644
--- a/src/freedreno/ir3/ir3_parser.y
+++ b/src/freedreno/ir3/ir3_parser.y
@@ -705,14 +705,17 @@ mova_src:          src_reg_or_const_or_rel
 |                  immediate_cat1
 |                  src_reg_flags immediate_cat1
 
-cat1_mova1:        T_OP_MOVA1 T_A1 ',' {
+cat1_mova_flags:
+|                  '.' 'u' { iflags.flags |= IR3_INSTR_U; }
+
+cat1_mova1:        T_OP_MOVA1 cat1_mova_flags T_A1 ',' {
                        new_instr(OPC_MOV);
                        instr->cat1.src_type = TYPE_U16;
                        instr->cat1.dst_type = TYPE_U16;
                        new_dst((61 << 3) + 2, IR3_REG_HALF);
                    } mova_src
 
-cat1_mova:         T_OP_MOVA T_A0 ',' {
+cat1_mova:         T_OP_MOVA cat1_mova_flags T_A0 ',' {
                        new_instr(OPC_MOV);
                        instr->cat1.src_type = TYPE_S16;
                        instr->cat1.dst_type = TYPE_S16;
diff --git a/src/freedreno/ir3/tests/disasm.c b/src/freedreno/ir3/tests/disasm.c
index bdd28a2fedb..65fd17954fb 100644
--- a/src/freedreno/ir3/tests/disasm.c
+++ b/src/freedreno/ir3/tests/disasm.c
@@ -96,6 +96,9 @@ static const struct test {
    INSTR_6XX(20400006_00003800, "mov.f16f16 hr1.z, h(0.500000)"),
    INSTR_6XX(204880f5_00000000, "mova1 a1.x, 0"),
 
+   INSTR_6XX(201108f4_00000000, "mova.u a0.x, (r)hr0.x"),
+   INSTR_6XX(204888f5_00000000, "mova1.u a1.x, 0"),
+
    INSTR_7XX(2004c005_00000405, "cov.f32u32 r1.y, (last)r1.y"),
 
    INSTR_7XX(200440c0_ae800004, "movs.f32f32 r48.x, r1.x, 93"),
diff --git a/src/freedreno/isa/ir3-cat1.xml b/src/freedreno/isa/ir3-cat1.xml
index 5566550878e..f9c4fe7320e 100644
--- a/src/freedreno/isa/ir3-cat1.xml
+++ b/src/freedreno/isa/ir3-cat1.xml
@@ -77,7 +77,8 @@ SOFTWARE.
 	<pattern low="61" high="63">001</pattern>  <!-- cat1 -->
 	<encode>
 		<map name="SRC">src->srcs[0]</map>
-		<map name="SRC_R">!!(src->srcs[0]->flags &amp; IR3_REG_R)</map>
+		<!-- SRC_R doubles as the .u bit for mova/mova1: -->
+		<map name="SRC_R">!!(src->srcs[0]->flags &amp; IR3_REG_R) || !!(src->flags &amp; IR3_INSTR_U)</map>
 		<map name="UL">!!(src->flags &amp; IR3_INSTR_UL)</map>
 		<map name="DST_REL">!!(src->dsts[0]->flags &amp; IR3_REG_RELATIV)</map>
 		<map name="ROUND">src->cat1.round</map>
@@ -119,7 +120,7 @@ SOFTWARE.
 			({DST} == 0xf4 /* a0.x */) &amp;&amp; ({SRC_TYPE} == 4 /* s16 */) &amp;&amp; ({DST_TYPE} == 4)
 		</expr>
 		<display>
-			{SY}{SS}{JP}{REPEAT}{UL}mova {ROUND}{DM}a0.x, {SRC_R}{SRC}
+			{SY}{SS}{JP}{REPEAT}{UL}mova{U} {ROUND}{DM}a0.x, {SRC}
 		</display>
 		<assert low="32" high="39">11110100</assert>  <!-- DST==a0.x -->
 		<assert low="46" high="48">100</assert>       <!-- DST_TYPE==s16 -->
@@ -130,7 +131,7 @@ SOFTWARE.
 			({DST} == 0xf5 /* a0.y */) &amp;&amp; ({SRC_TYPE} == 2 /* u16 */) &amp;&amp; ({DST_TYPE} == 2)
 		</expr>
 		<display>
-			{SY}{SS}{JP}{REPEAT}{UL}mova1 {ROUND}{DM}a1.x, {SRC_R}{SRC}
+			{SY}{SS}{JP}{REPEAT}{UL}mova1{U} {ROUND}{DM}a1.x, {SRC}
 		</display>
 		<assert low="32" high="39">11110101</assert>  <!-- DST==a0.y -->
 		<assert low="46" high="48">010</assert>       <!-- DST_TYPE==u16 -->
@@ -147,6 +148,9 @@ SOFTWARE.
 	<display>
 		{SY}{SS}{JP}{REPEAT}{UL}mov.{SRC_TYPE}{DST_TYPE} {ROUND}{DM}{DST_HALF}{DST}, {SRC}
 	</display>
+	<derived name="U" type="bool" display=".u">
+		<expr>{SRC_R}</expr>
+	</derived>
 	<field name="DST" low="32" high="39" type="#cat1-dst">
 		<param name="DST_REL"/>
 	</field>