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radeonsi/gfx9: fix the scissor bug workaround

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otherwise there is corruption in most apps.

Fixes: 0fe0320 radeonsi: use optimal packet order when doing a pipeline sync

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-08-10 21:50:59 +02:00
parent 27fef5d52d
commit d1285a7103
1 changed files with 7 additions and 3 deletions
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10
src/gallium/drivers/radeonsi/si_state_draw.c
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@ -1368,11 +1368,15 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
if (!si_upload_vertex_buffer_descriptors(sctx))
return;
/* GFX9 scissor bug workaround. There is also a more efficient but
* more involved alternative workaround. */
/* GFX9 scissor bug workaround. This must be done before VPORT scissor
* registers are changed. There is also a more efficient but more
* involved alternative workaround.
*/
if (sctx->b.chip_class == GFX9 &&
si_is_atom_dirty(sctx, &sctx->b.scissors.atom))
si_is_atom_dirty(sctx, &sctx->b.scissors.atom)) {
sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
si_emit_cache_flush(sctx);
}
/* Use optimal packet order based on whether we need to sync the pipeline. */
if (unlikely(sctx->b.flags & (SI_CONTEXT_FLUSH_AND_INV_CB |